feat(rp2040): add missing opcodeXXX #18
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During debugging I found sometimes the LR register has LSB reset to 0 while on a real Pico at the same position it is always set as 1. This also matches the armv6-m reference manual pag 113-114.
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Thank you! Can you also update the tests (rp2040.spec.ts) to use these functions instead of the hard-coded opcodes? |
Turro75
commented
May 11, 2021
src/instructions.spec.ts
Outdated
| @@ -809,7 +825,7 @@ describe('Cortex-M0+ Instruction Set', () => { | |||
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| it('should execute a `lsls r5, r5, #18` instruction with carry', async () => { | |||
| await cpu.setPC(0x20000000); | |||
| await cpu.writeUint16(0x20000000, 0x04ad); // lsls r5, r5, #18 | |||
| await cpu.writeUint16(0x20000000, opcodeLSLSimm(r5,r5,18)); //)0x04ad); // lsls r5, r5, #18 | |||
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This one has carry (see the last assertion in this test)
urish
reviewed
May 11, 2021
src/instructions.spec.ts
Outdated
| @@ -786,7 +802,7 @@ describe('Cortex-M0+ Instruction Set', () => { | |||
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| it('should execute a `lsls r5, r5, #18` instruction', async () => { | |||
| await cpu.setPC(0x20000000); | |||
| await cpu.writeUint16(0x20000000, 0x04ad); // lsls r5, r5, #18 | |||
| await cpu.writeUint16(0x20000000, opcodeLSLSimm(r5,r5,18));// 0x04ad); // lsls r5, r5, #18 | |||
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Can you also remove the comment with the opcode at the end of the line?
We no longer need those since you can see the name and arguments of the opcode in the function call
urish
added a commit
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May 13, 2021
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