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feat(rp2040): add missing opcodeXXX #18

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merged 7 commits into from
May 11, 2021
Merged

feat(rp2040): add missing opcodeXXX #18

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5b4091f
LR LSB must be always 1
Turro75 May 4, 2021
520c364
Merge branch 'wokwi:master' into master
Turro75 May 11, 2021
077db5c
feat (rp2040js): add missing opcodeXXX
Turro75 May 11, 2021
1c722f1
feat(rp2040): add opcode B T1 & T2
Turro75 May 11, 2021
b1cccd4
test(rp2040): implement opcode in all test
Turro75 May 11, 2021
8041ccb
test(rp2040): useless comments / console.log removal on instructions
Turro75 May 11, 2021
3701f8d
fix previous commit
Turro75 May 11, 2021
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50 changes: 33 additions & 17 deletions src/instructions.spec.ts
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Original file line number Diff line number Diff line change
Expand Up @@ -14,30 +14,43 @@ import {
opcodeBICS,
opcodeBL,
opcodeBLX,
opcodeBT1,
opcodeBT2,
opcodeBX,
opcodeCMN,
opcodeCMPimm,
opcodeCMPregT1,
opcodeCMPregT2,
opcodeDMBSY,
opcodeDSBSY,
opcodeEORS,
opcodeISBSY,
opcodeLDMIA,
opcodeLDRB,
opcodeLDRBreg,
opcodeLDRH,
opcodeLDRHreg,
opcodeLDRimm,
opcodeLDRlit,
opcodeLDRreg,
opcodeLDRSB,
opcodeLDRSH,
opcodeLDRsp,
opcodeLSLSimm,
opcodeLSLSreg,
opcodeLSRS,
opcodeLSRSreg,
opcodeMOV,
opcodeMOVS,
opcodeMOVSreg,
opcodeMRS,
opcodeMSR,
opcodeMULS,
opcodeMVNS,
opcodeNOP,
opcodeORRS,
opcodePOP,
opcodePUSH,
opcodeREV,
opcodeREV16,
opcodeREVSH,
Expand All @@ -59,6 +72,8 @@ import {
opcodeSVC,
opcodeSXTB,
opcodeSXTH,
opcodeTST,
opcodeUDF,
opcodeUDF2,
opcodeUXTB,
opcodeUXTH,
Expand Down Expand Up @@ -356,7 +371,8 @@ describe('Cortex-M0+ Instruction Set', () => {

it('should execute a `b.n .-20` instruction', async () => {
await cpu.setPC(0x20000000 + 9 * 2);
await cpu.writeUint16(0x20000000 + 9 * 2, 0xe7f6); // b.n .-20
console.log(opcodeBT2(0xfec).toString(16));
await cpu.writeUint16(0x20000000 + 9 * 2, opcodeBT2(0xfec)); //0xe7f6); // b.n .-20
await cpu.singleStep();
const registers = await cpu.readRegisters();
expect(registers.pc).toEqual(0x20000002);
Expand All @@ -365,7 +381,7 @@ describe('Cortex-M0+ Instruction Set', () => {
it('should execute a `bne.n .-6` instruction', async () => {
await cpu.setPC(0x20000000 + 9 * 2);
await cpu.setRegisters({ Z: false });
await cpu.writeUint16(0x20000000 + 9 * 2, 0xd1fc); // bne.n .-6
await cpu.writeUint16(0x20000000 + 9 * 2, opcodeBT1(1,0x1f8)); // 0xd1fc); // bne.n .-6
await cpu.singleStep();
const registers = await cpu.readRegisters();
expect(registers.pc).toEqual(0x2000000e);
Expand Down Expand Up @@ -397,7 +413,7 @@ describe('Cortex-M0+ Instruction Set', () => {

it('should execute an `cmp r5, #66` instruction', async () => {
await cpu.setPC(0x20000000);
await cpu.writeUint16(0x20000000, 0x2d42); // cmp r5, #66
await cpu.writeUint16(0x20000000, opcodeCMPimm(r5,66)); //0x2d42); // cmp r5, #66
await cpu.setRegisters({ r5: 60 });
await cpu.singleStep();
const registers = await cpu.readRegisters();
Expand All @@ -409,7 +425,7 @@ describe('Cortex-M0+ Instruction Set', () => {

it('should execute an `cmp r5, r0` instruction', async () => {
await cpu.setPC(0x20000000);
await cpu.writeUint16(0x20000000, 0x4285); // cmp r5, r0
await cpu.writeUint16(0x20000000, opcodeCMPregT1(r5,r0));// 0x4285 // cmp r5, r0
await cpu.setRegisters({ r5: 60 });
await cpu.setRegisters({ r0: 56 });
await cpu.singleStep();
Expand All @@ -422,7 +438,7 @@ describe('Cortex-M0+ Instruction Set', () => {

it('should execute an `cmp ip, r6` instruction', async () => {
await cpu.setPC(0x20000000);
await cpu.writeUint16(0x20000000, 0x45b4); // cmp ip (r12), r6
await cpu.writeUint16(0x20000000, opcodeCMPregT2(ip,r6));// 0x45b4); // cmp ip (r12), r6
await cpu.setRegisters({ r6: 56, r12: 60 });
await cpu.singleStep();
const registers = await cpu.readRegisters();
Expand All @@ -434,15 +450,15 @@ describe('Cortex-M0+ Instruction Set', () => {

it('should correctly decode a `dmb sy` instruction', async () => {
await cpu.setPC(0x20000000);
await cpu.writeUint32(0x20000000, 0x8f50f3bf); // DMB SY
await cpu.writeUint32(0x20000000, opcodeDMBSY());//0x8f50f3bf // DMB SY
await cpu.singleStep();
const registers = await cpu.readRegisters();
expect(registers.pc).toBe(0x20000004);
});

it('should correctly decode a `dsb sy` instruction', async () => {
await cpu.setPC(0x20000000);
await cpu.writeUint32(0x20000000, 0x8f4ff3bf); // DSB SY
await cpu.writeUint32(0x20000000, opcodeDSBSY());// 0x8f4ff3bf // DSB SY
await cpu.singleStep();
const registers = await cpu.readRegisters();
expect(registers.pc).toBe(0x20000004);
Expand All @@ -462,7 +478,7 @@ describe('Cortex-M0+ Instruction Set', () => {

it('should correctly decode a `isb sy` instruction', async () => {
await cpu.setPC(0x20000000);
await cpu.writeUint32(0x20000000, 0x8f6ff3bf); // ISB SY
await cpu.writeUint32(0x20000000, opcodeISBSY());//0x8f6ff3bf // ISB SY
await cpu.singleStep();
const registers = await cpu.readRegisters();
expect(registers.pc).toBe(0x20000004);
Expand Down Expand Up @@ -583,7 +599,7 @@ describe('Cortex-M0+ Instruction Set', () => {
it('should execute a `push {r4, r5, r6, lr}` instruction', async () => {
await cpu.setPC(0x20000000);
await cpu.setRegisters({ sp: RAM_START_ADDRESS + 0x100 });
await cpu.writeUint16(0x20000000, 0xb570); // push {r4, r5, r6, lr}
await cpu.writeUint16(0x20000000, opcodePUSH(true,(1 << r4) | (1 << r5) | (1 << r6)));// 0xb570 // push {r4, r5, r6, lr}
await cpu.setRegisters({ r4: 0x40, r5: 0x50, r6: 0x60, lr: 0x42 });
await cpu.singleStep();
const registers = await cpu.readRegisters();
Expand Down Expand Up @@ -651,7 +667,7 @@ describe('Cortex-M0+ Instruction Set', () => {

it('should execute an `ldr r0, [pc, #148]` instruction', async () => {
await cpu.setPC(0x20000000);
await cpu.writeUint16(0x20000000, 0x4825); // ldr r0, [pc, #148]
await cpu.writeUint16(0x20000000, opcodeLDRlit(r0,148)); // 0x4825); // ldr r0, [pc, #148]
await cpu.writeUint32(0x20000000 + 152, 0x42);
await cpu.singleStep();
const registers = await cpu.readRegisters();
Expand All @@ -661,7 +677,7 @@ describe('Cortex-M0+ Instruction Set', () => {

it('should execute an `ldr r3, [r2, #24]` instruction', async () => {
await cpu.setPC(0x20000000);
await cpu.writeUint16(0x20000000, 0x6993); // ldr r3, [r2, #24]
await cpu.writeUint16(0x20000000,opcodeLDRimm(r3,r2,24)); // 0x6993 // ldr r3, [r2, #24]
await cpu.setRegisters({ r2: 0x20000000 });
await cpu.writeUint8(0x20000000 + 24, 0x55);
await cpu.singleStep();
Expand Down Expand Up @@ -766,7 +782,7 @@ describe('Cortex-M0+ Instruction Set', () => {
const breakMock = jest.fn();
const rp2040 = new RP2040();
rp2040.PC = 0x20000000;
rp2040.writeUint16(0x20000000, 0xde01); // udf 1
rp2040.writeUint16(0x20000000, opcodeUDF(0x1)); //0xde01 // udf 1
rp2040.onBreak = breakMock;
rp2040.executeInstruction();
expect(rp2040.PC).toEqual(0x20000002);
Expand All @@ -786,7 +802,7 @@ describe('Cortex-M0+ Instruction Set', () => {

it('should execute a `lsls r5, r5, #18` instruction', async () => {
await cpu.setPC(0x20000000);
await cpu.writeUint16(0x20000000, 0x04ad); // lsls r5, r5, #18
await cpu.writeUint16(0x20000000, opcodeLSLSimm(r5,r5,18));// 0x04ad); // lsls r5, r5, #18
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Can you also remove the comment with the opcode at the end of the line?

We no longer need those since you can see the name and arguments of the opcode in the function call

await cpu.setRegisters({ r5: 0b00000000000000000011 });
await cpu.singleStep();
const registers = await cpu.readRegisters();
Expand All @@ -809,7 +825,7 @@ describe('Cortex-M0+ Instruction Set', () => {

it('should execute a `lsls r5, r5, #18` instruction with carry', async () => {
await cpu.setPC(0x20000000);
await cpu.writeUint16(0x20000000, 0x04ad); // lsls r5, r5, #18
await cpu.writeUint16(0x20000000, opcodeLSLSimm(r5,r5,18)); //)0x04ad); // lsls r5, r5, #18
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duplicated test?

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This one has carry (see the last assertion in this test)

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ok

await cpu.setRegisters({ r5: 0x00004001 });
await cpu.singleStep();
const registers = await cpu.readRegisters();
Expand Down Expand Up @@ -853,7 +869,7 @@ describe('Cortex-M0+ Instruction Set', () => {

it('should execute a `movs r6, r5` instruction', async () => {
await cpu.setPC(0x20000000);
await cpu.writeUint16(0x20000000, 0x002e); // movs r6, r5
await cpu.writeUint16(0x20000000, opcodeMOVSreg(r6,r5));// 0x002e // movs r6, r5
await cpu.setRegisters({ r5: 0x50 });
await cpu.singleStep();
const registers = await cpu.readRegisters();
Expand Down Expand Up @@ -1154,7 +1170,7 @@ describe('Cortex-M0+ Instruction Set', () => {

it('should execute an `tst r1, r3` instruction when the result is negative', async () => {
await cpu.setPC(0x20000000);
await cpu.writeUint16(0x20000000, 0x4219); // tst r1, r3
await cpu.writeUint16(0x20000000, opcodeTST(r1,r3)); //0x4219 // tst r1, r3
await cpu.setRegisters({ r1: 0xf0000000 });
await cpu.setRegisters({ r3: 0xf0004000 });
await cpu.singleStep();
Expand All @@ -1164,7 +1180,7 @@ describe('Cortex-M0+ Instruction Set', () => {

it('should execute an `tst r1, r3` instruction when the registers are different', async () => {
await cpu.setPC(0x20000000);
await cpu.writeUint16(0x20000000, 0x4219); // tst r1, r3
await cpu.writeUint16(0x20000000, opcodeTST(r1,r3)); // 0x4219 // tst r1, r3
await cpu.setRegisters({ r1: 0xf0, r3: 0x0f });
await cpu.singleStep();
const registers = await cpu.readRegisters();
Expand Down