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fix(rp2040): Fix CMP reg T1 #31

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merged 9 commits into from
May 16, 2021
Merged

fix(rp2040): Fix CMP reg T1 #31

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f8cca9e
fix(rp2040): SBCS xPSR Flags Handling
Turro75 May 16, 2021
86b496a
Revert "fix(rp2040): SBCS xPSR Flags Handling"
Turro75 May 16, 2021
867a464
fix(rp2040): Fix SBCS flags handling
Turro75 May 16, 2021
f677321
Revert "fix(rp2040): Fix SBCS flags handling"
Turro75 May 16, 2021
5c39f36
fix(rp2040): Fix SBCS flags handling
Turro75 May 16, 2021
0cdd227
fix(rp2040): CMP reg T1 Carry handling
Turro75 May 16, 2021
fece811
refactor as requested
Turro75 May 16, 2021
8fab43a
set more specific name to added cmp test
Turro75 May 16, 2021
bc84358
equalize test name like other
Turro75 May 16, 2021
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25 changes: 25 additions & 0 deletions src/instructions.spec.ts
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Original file line number Diff line number Diff line change
Expand Up @@ -469,6 +469,18 @@ describe('Cortex-M0+ Instruction Set', () => {
expect(registers.V).toEqual(false);
});

it('should execute an cmp r2, r0 instruction and not set any flags when r0=0xb71b0000 and r2=0x00b71b00', async () => {
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Ok, one more small thing: please add backticks (`) around the instruction name, like in the other tests

await cpu.setPC(0x20000000);
await cpu.writeUint16(0x20000000, opcodeCMPregT1(r2, r0));
await cpu.setRegisters({ r0: 0xb71b0000, r2: 0x00b71b00 });
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await cpu.singleStep();
const registers = await cpu.readRegisters();
expect(registers.N).toEqual(false);
expect(registers.Z).toEqual(false);
expect(registers.C).toEqual(false);
expect(registers.V).toEqual(false);
});
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it('should correctly set carry flag when executing `cmp r11, r3` instruction', async () => {
await cpu.setPC(0x20000000);
await cpu.writeUint16(0x20000000, opcodeCMPregT2(r11, r3));
Expand Down Expand Up @@ -1055,6 +1067,19 @@ describe('Cortex-M0+ Instruction Set', () => {
expect(registers.V).toEqual(false);
});

it('should execute a `sbcs r0, r3` instruction', async () => {
await cpu.setPC(0x20000000);
await cpu.writeUint16(0x20000000, opcodeSBCS(r0, r3));
await cpu.setRegisters({ r0: 0, r3: 0xffffffff, C: false });
await cpu.singleStep();
const registers = await cpu.readRegisters();
expect(registers.r0).toEqual(0);
expect(registers.N).toEqual(false);
expect(registers.Z).toEqual(true);
expect(registers.C).toEqual(false);
expect(registers.V).toEqual(false);
});

it('should execute a `sdmia r0!, {r1, r2}` instruction', async () => {
await cpu.setPC(0x20000000);
await cpu.writeUint16(0x20000000, opcodeSTMIA(r0, (1 << r1) | (1 << r2)));
Expand Down
14 changes: 7 additions & 7 deletions src/rp2040.ts
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Original file line number Diff line number Diff line change
Expand Up @@ -1028,10 +1028,10 @@ export class RP2040 {
else if (opcode >> 6 === 0b0100001010) {
const Rm = (opcode >> 3) & 0x7;
const Rn = opcode & 0x7;
const leftValue = this.registers[Rn] | 0;
const rightValue = this.registers[Rm] | 0;
const result = (leftValue - rightValue) | 0;
this.N = leftValue < rightValue;
const leftValue = this.registers[Rn];
const rightValue = this.registers[Rm];
const result = ((leftValue | 0) - (rightValue | 0)) | 0;
this.N = result < 0;
this.Z = leftValue === rightValue;
this.C = leftValue >= rightValue;
this.V =
Expand Down Expand Up @@ -1410,16 +1410,16 @@ export class RP2040 {
else if (opcode === 0b1011111100000000) {
// Do nothing!
}
// SBCS (Encoding T2)
// SBCS (Encoding T1)
else if (opcode >> 6 === 0b0100000110) {
const Rm = (opcode >> 3) & 0x7;
const Rdn = opcode & 0x7;
const operand1 = this.registers[Rdn];
const operand2 = this.registers[Rm] + (this.C ? 0 : 1);
const result = (operand1 - operand2) | 0;
this.registers[Rdn] = result;
this.N = operand1 < operand2;
this.Z = operand1 === operand2;
this.N = (operand1 | 0) < (operand2 | 0);
this.Z = (operand1 | 0) === (operand2 | 0);
this.C = operand1 >= operand2;
this.V = (operand1 | 0) < 0 && operand2 > 0 && result > 0;
}
Expand Down