Update 5.4-2.3.x-imx to NXP [rel_imx_5.4.70_2.3.2] tag #317
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There are cases when the interrupt status register (JRINTR) is non-zero, even though there was no interrupt generated for the corresponding job ring. For example JRINTR=0x0000_0008 - i.e. JRINTR[HALT]=b'10 - indicates that the input job ring underwent a flush of all on-going jobs and processing of still-existing jobs (sitting in the ring) has been halted. This doesn't mean there's currently anything to do for this job ring. Make sure the shared IRQ line is correctly handled by updating the condition for returning IRQ_NONE, otherwise we could reach situations like: 1. interrupt handler clearing JRINTR (and thus also the JRINTR[HALT] field) while corresponding job ring is suspended and then 2. that job ring failing on resume path, due to expecting JRINTR[HALT]=b'10 and reading instead JRINTR[HALT]=b'00. Signed-off-by: Horia Geantă <[email protected]> Reviewed-by: Franck LENORMAND <[email protected]> (cherry picked from commit 905aeea) Signed-off-by: Andrey Zhizhikin <[email protected]>
Interrupts may happen right after imx_rproc_xtr_mbox_init(), init the priv->rproc_work before imx_rproc_xtr_mbox_init() to avoid panic in such case. Test: Trigger panic via sysrq-trigger. Change-Id: Idab25a9e97acf9649f9d570ad6bea511a8a94b67 Suggested-by: Peng Fan <[email protected]> Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Ji Luo <[email protected]> (cherry picked from commit e2bb921) Signed-off-by: Andrey Zhizhikin <[email protected]>
Set the value of SS1-SS0 and SF3-SF0 to zero to pass CTS 7-30. Signed-off-by: Sandor Yu <[email protected]> Reviewed-by: Shengjiu Wang <[email protected]> (cherry picked from commit 63d09a7) Signed-off-by: Andrey Zhizhikin <[email protected]>
reset hdmi phy power. Signed-off-by: Sandor Yu <[email protected]> Reviewed-by: Robby Cai <[email protected]> (cherry picked from commit a078ede) Signed-off-by: Andrey Zhizhikin <[email protected]>
Fine tune hdmi phy to pass HDMI electrical CTS. Signed-off-by: Sandor Yu <[email protected]> Reviewed-by: Robby Cai <[email protected]> (cherry picked from commit 14621f1) Signed-off-by: Andrey Zhizhikin <[email protected]>
EXP2_INT_B is low when evk power on and it is hight when press reset botton. U84 PCA6416 have not reset correct when board power on. Reset it by toggle I2C_EXP4_P0.2 [ 55.885169] irq 162: nobody cared (try booting with the "irqpoll" option) [ 55.891980] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.4.70-2.3.0+g4f2631b022d8 Freescale#1 [ 55.899641] Hardware name: Freescale i.MX8DXL EVK (DT) [ 55.904784] Call trace: [ 55.907244] dump_backtrace+0x0/0x140 [ 55.910911] show_stack+0x14/0x20 [ 55.914233] dump_stack+0xb4/0x114 [ 55.917638] __report_bad_irq+0x48/0xd4 [ 55.921475] note_interrupt+0x2c4/0x388 [ 55.925318] handle_irq_event_percpu+0x80/0x88 [ 55.929762] handle_irq_event+0x44/0xd8 [ 55.933603] handle_level_irq+0xb4/0x138 [ 55.937531] generic_handle_irq+0x24/0x38 [ 55.941547] mxc_gpio_irq_handler+0x48/0x138 [ 55.945817] mx3_gpio_irq_handler+0x80/0xe8 [ 55.950004] generic_handle_irq+0x24/0x38 [ 55.954020] __handle_domain_irq+0x60/0xb8 [ 55.958120] gic_handle_irq+0x5c/0x148 [ 55.961872] el1_irq+0xb8/0x180 [ 55.965019] arch_cpu_idle+0x10/0x18 [ 55.968598] do_idle+0x200/0x280 [ 55.971826] cpu_startup_entry+0x24/0x80 [ 55.975756] rest_init+0xd4/0xe0 [ 55.978989] arch_call_rest_init+0xc/0x14 [ 55.982998] start_kernel+0x418/0x44c Signed-off-by: Frank Li <[email protected]> (cherry picked from commit 7dd0691) Signed-off-by: Andrey Zhizhikin <[email protected]>
I2c chip are reset when the partition reboots. A partition reboot has to reset the ones used by a specific OS. Signed-off-by: Frank Li <[email protected]> (cherry picked from commit 3362e48) Signed-off-by: Andrey Zhizhikin <[email protected]>
In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from external OSC or internal system PLL. It is configured in the IOMUX_GPR14 register directly, and can't be contolled by CCM at all. So, correct it in the DTS node. Signed-off-by: Richard Zhu <[email protected]> Reviewed-by: Jason Liu <[email protected]> (cherry picked from commit 65b5b8974b14cc4fee501310e97e675eda4f4e1b) (cherry picked from commit db6a520) Signed-off-by: Andrey Zhizhikin <[email protected]>
In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from external OSC or internal system PLL. It is configured in the IOMUX_GPR14 register directly, and can't be contolled by CCM at all. Remove it from clock driver to clean up codes. Signed-off-by: Richard Zhu <[email protected]> Reviewed-by: Jason Liu <[email protected]> (cherry picked from commit 631360d6ba454aa9180325d73c12523a45946a51) (cherry picked from commit 24e3536) Signed-off-by: Andrey Zhizhikin <[email protected]>
Add one clkreq reset to support the L1sub for i.MX8M PCIe. Signed-off-by: Richard Zhu <[email protected]> Reviewed-by: Jun Li <[email protected]> (cherry picked from commit 3ac7bf70f9cda0f25b8d94678e5bbbd70c387b2f) (cherry picked from commit 3b776f7) Signed-off-by: Andrey Zhizhikin <[email protected]>
fix the clkreq# is always low issue when L1.1 ASPM is enabled. Signed-off-by: Richard Zhu <[email protected]> Reviewed-by: Jun Li <[email protected]> (cherry picked from commit 6c3f41636a97d020aad4d4ebb43c6b9f6f9ddcb4) (cherry picked from commit a661f2f) Signed-off-by: Andrey Zhizhikin <[email protected]>
…operty Set the PCIe CLKREQ# as input and add the num-viewport property for i.MX8MP PCIe RC port. Signed-off-by: Richard Zhu <[email protected]> Reviewed-by: Jun Li <[email protected]> (cherry picked from commit f95d91816f5d521b2dec5fa2fe7f2a52a381eded) (cherry picked from commit 8a5e146) Signed-off-by: Andrey Zhizhikin <[email protected]>
Add one final quirk to adjust the l1ss support to proper place. Only enable the L1sub support when both RC and EP supports the L1sub. In this case, remove the over-ride of the CLKREQ# signal, let HW to control it automatically. Since "dis_gpio" GPIO pin is used as M.2 Key-E interface PIN56 for power control of EP device, adjust active sequence just after the turn-on of the power domains. Signed-off-by: Richard Zhu <[email protected]> Reviewed-by: Jun Li <[email protected]> (cherry picked from commit 02f7efffe67332a4daacae732cccd012d4cbf9db) (cherry picked from commit 9a6ced7) Signed-off-by: Andrey Zhizhikin <[email protected]>
Set the parent clock for PCIE_AUX clock firstly, then set the rate of the PCI_AUX clock to 10MHZ. Signed-off-by: Richard Zhu <[email protected]> Reviewed-by: Peter Chen <[email protected]> (cherry picked from commit c787efe575330e538cc92da0dde49255bdc80c94) (cherry picked from commit 855ad0c) Signed-off-by: Andrey Zhizhikin <[email protected]>
The sys2_pll_50m should be one of the clock sels of PCIE_AUX clock, otherwise the sys2_pll_500m. Signed-off-by: Richard Zhu <[email protected]> Reviewed-by: Peter Chen <[email protected]> (cherry picked from commit 0af1467f5c58229c8220d54d38ce9b6152361387) (cherry picked from commit 8855188) Signed-off-by: Andrey Zhizhikin <[email protected]>
Upgrade to mxm5x16215 verison: - Updated driver to request pm_qos only in connected state Signed-off-by: Sherry Sun <[email protected]> Approved-by: yang.tian <[email protected]> (cherry picked from commit b8d23738835be6e88562f1afd92cca7afb7c6c22) (cherry picked from commit 0cd055b) Signed-off-by: Andrey Zhizhikin <[email protected]>
…elease Upgrade to mxm5x16215 verison: - Fixed compilation warning seen when compiling for 32-bit systems - Fixed VTS/CTS regression test failure - WCSWREL-99 Fixed host_mlme = disable print issue even when host_mlme=1 was given Signed-off-by: Sherry Sun <[email protected]> Reviewed-by: yang.tian <[email protected]> (cherry picked from commit d12e2f02e1e852bb66176a64baa369e70997e2bc) (cherry picked from commit 634914e) Signed-off-by: Andrey Zhizhikin <[email protected]>
…elease Upgrade to mxm5x16215 verison: - None Signed-off-by: Sherry Sun <[email protected]> Approved-by: yang.tian <[email protected]> (cherry picked from commit 03c91af0b7784450a38ebb1211ac73811b735f30) (cherry picked from commit 4564926) Signed-off-by: Andrey Zhizhikin <[email protected]>
on iMX8MP, there's only 1 dewarp. the patch adds a second dewarp node (virtual) to work with ISP SW release P8. this might be removed after vendor modify the way using dewarp. Signed-off-by: Robby Cai <[email protected]> Reviewed-by: Guoniu.zhou <[email protected]> (cherry picked from commit 3c32b1080083faff8381cdeb1adadaff0144aac3) (cherry picked from commit b16c09a) Signed-off-by: Andrey Zhizhikin <[email protected]>
enable the virtual dewarp to work with ISP SW release P8. Signed-off-by: Robby Cai <[email protected]> Reviewed-by: Guoniu.zhou <[email protected]> (cherry picked from commit 0fff98516a430952b97102053c438d1ab27c97a1) (cherry picked from commit 15b0588) Signed-off-by: Andrey Zhizhikin <[email protected]>
…v2775 add dual isp supports with basler camera and ov2775 Signed-off-by: Robby Cai <[email protected]> Reviewed-by: Guoniu.zhou <[email protected]> (cherry picked from commit 2bd39f91a47ad50981f96dd46b1f9e50a0cc0266) (cherry picked from commit af20fa8) Signed-off-by: Andrey Zhizhikin <[email protected]>
add dual baslers camera support to work with dual ISPs Signed-off-by: Robby Cai <[email protected]> Reviewed-by: Guoniu.zhou <[email protected]> (cherry picked from commit a755ce242b551dafcca648f9d54585fd9ba02493) (cherry picked from commit b8ac5f3) Signed-off-by: Andrey Zhizhikin <[email protected]>
Set MIPI clock according to IC team. for 1 ISP camera on CSI0, MIPI CSI clock set to 500MHz for 2 ISP cameras on CSI0/CSI1, MIPI CSI clock both set to 266MHz Signed-off-by: Robby Cai <[email protected]> Reviewed-by: Guoniu.zhou <[email protected]> (cherry picked from commit a38f457b63fa8a0d9b4c5de39a12959c172e7e35) (cherry picked from commit e20ebbc) Signed-off-by: Andrey Zhizhikin <[email protected]>
update ISP and Dewarp clock and power Signed-off-by: Robby Cai <[email protected]> Reviewed-by: Guoniu.zhou <[email protected]> (cherry picked from commit e6031680ba2d67a6961a5da5fc68a913962c66d2) (cherry picked from commit f5390f2) Signed-off-by: Andrey Zhizhikin <[email protected]>
second virtual dewarp node not needed as VSI gets back to use the real dewarp Signed-off-by: Robby Cai <[email protected]> Reviewed-by: Guoniu.zhou <[email protected]> (cherry picked from commit bf7698bb60035c7b32cec6f7c57e3072869a7888) (cherry picked from commit 420d04d) Signed-off-by: Andrey Zhizhikin <[email protected]>
Previously it controls dewarp in mipi driver which is not standard way. Now use gpr to control dewarp in dewarp driver. Signed-off-by: Robby Cai <[email protected]> Reviewed-by: Guoniu.zhou <[email protected]> (cherry picked from commit 22373bd4b6979bc9c8e63b678bcd5204714fd4c9) (cherry picked from commit 7db1a36) Signed-off-by: Andrey Zhizhikin <[email protected]>
use memory-region to get reserved memory Signed-off-by: Robby Cai <[email protected]> Reviewed-by: Guoniu.zhou <[email protected]> (cherry picked from commit 5a28380ef4f4afffdabcfacd062706487cc150f8) (cherry picked from commit 9a75296) Signed-off-by: Andrey Zhizhikin <[email protected]>
…ed MIPI clock for 1 ISP camera on CSI0, MIPI CSI clock set to 500MHz for 2 ISP cameras on CSI0/CSI1, MIPI CSI clock both set to 266MHz Basler camera driver uses link-frequencies to retrieve proper clocks on 1 ISP or 2 ISP cameras cases. Originally from Thies Moeller <[email protected]> Signed-off-by: Robby Cai <[email protected]> Reviewed-by: Guoniu.zhou <[email protected]> (cherry picked from commit bb98a98727e49cc40539be66c5f7aefc8e6009b9) (cherry picked from commit 21c3114) Signed-off-by: Andrey Zhizhikin <[email protected]>
Coverity Issue: 10436670, 10893372, 10436673, fix string overflow issue. The length of v4l2_capability structure driver member is 16, but the length of "csi_samsung_subdev" is 18, when assign it to driver member, it will occur string overflow issue. Signed-off-by: Guoniu.zhou <[email protected]> Reviewed-by: Robby Cai <[email protected]> (cherry picked from commit b4ffa85521e12cf02fb22e955331c0b1355ee219) (cherry picked from commit 0ff86d2) Signed-off-by: Andrey Zhizhikin <[email protected]>
…ssue
Refine commit 17db82300f80 ("MLK-25089 phy: freescale: pcie: fix the
imx8mp evk ep rc link speed issue")
Fine tune the PHY parameters, let the PCIe link up to GEN3 between two
i.MX865 EVK boards in the i.MX EP RC validation system.
Since this fine tuned is only specified for EVK boards. Add the command
parameter to specify it when do the EP RC tests between two i.MX8MP EVK
boards. Use the "pcie_phy_tuned=yes" to enable the PHY fine-tune.
Signed-off-by: Richard Zhu <[email protected]>
Reviewed-by: Peter Chen <[email protected]>
(cherry picked from commit 2ab5581a1448bf24a37f8082ffe725a54ce09b5e)
(cherry picked from commit fd8e0e4)
Signed-off-by: Andrey Zhizhikin <[email protected]>
The commit af20fa8 introduced a break when cherry-pick from mainline. make[3]: *** No rule to make target 'arch/arm64/boot/dts/freescale/imx8mp-evk-iqaudio-dacplus.dtb', needed by '__build'. Stop. make[3]: *** Waiting for unfinished jobs.... DTC arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dtb make[2]: *** [../scripts/Makefile.build:500: arch/arm64/boot/dts/freescale] Error 2 make[1]: *** [/home/nxa14866/ProjectA/linux-imx_bk/Makefile:1269: dtbs] Error 2 make[1]: Leaving directory '/home/nxa14866/ProjectA/linux-imx_bk/build_v8' make: *** [Makefile:179: sub-make] Error 2 The patch removed build for imx8mp-evk-iqaudio-dacplus.dtb because it's not in this branch. Signed-off-by: Robby Cai <[email protected]> (cherry picked from commit aa26d4f) Signed-off-by: Andrey Zhizhikin <[email protected]>
dma API(s) can't use NULL device because of following patch: d7e02a9 dma-mapping: remove leftover NULL device support this patch uses pxp_dev instead of NULL device to resolve kernel dump. [ 445.484900] 8<--- cut here --- [ 445.488002] Unable to handle kernel NULL pointer dereference at virtual address 0000015c [ 445.512965] pgd = 2afadd37 [ 445.515707] [0000015c] *pgd=00000000 [ 445.521436] Internal error: Oops: 5 [Freescale#1] PREEMPT SMP ARM [ 445.526776] Modules linked in: 8021q mx6s_capture ov5640_camera_v2 [ 445.532993] CPU: 0 PID: 2117 Comm: vqueue:src Not tainted 5.4.70-2.3.0+g4f2631b022d8 Freescale#1 [ 445.541006] Hardware name: Freescale i.MX6 Ultralite (Device Tree) [ 445.547214] PC is at pxp_device_ioctl+0xc64/0xe80 [ 445.551933] LR is at pxp_buffer_object_lookup+0x30/0x38 [ 445.557169] pc : [<80550e20>] lr : [<8054fd00>] psr: 60000013 [ 445.563446] sp : 93bffea8 ip : 908a03ac fp : 76957ff8 [ 445.568681] r10: 00000036 r9 : 93bfe000 r8 : 93b04540 [ 445.573917] r7 : 939d78c0 r6 : 80085007 r5 : 939d77c0 r4 : 00000000 [ 445.580454] r3 : 00000001 r2 : 00000000 r1 : 00000002 r0 : 939d77c0 [ 445.586993] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none [ 445.594140] Control: 10c5387d Table: 93bd806a DAC: 00000051 [ 445.599904] Process vqueue:src (pid: 2117, stack limit = 0xcf85841b) [ 445.606270] Stack: (0x93bffea8 to 0x93c00000) [ 445.610645] fea0: 73800000 8020a840 93ab8800 81304f08 739bc000 93ab8800 [ 445.618841] fec0: 93b8f840 739bc000 93b0fa80 8020eddc 93ab8800 00000002 00000001 00100c00 [ 445.627037] fee0: 00000000 93bffee8 00000000 81304f08 00000008 741d7ff4 926428d0 80085007 [ 445.635234] ff00: 741d7ff4 93b04540 93bfe000 00000036 76957ff8 80256c3c 93ab8800 0000010a [ 445.643430] ff20: 00000106 00000000 00000000 93b8f840 00000001 80210c20 000001e7 00000000 [ 445.651626] ff40: 0009a100 93b8f848 93bfff54 0001c200 93bfff7c 00000001 93b04540 0000000b [ 445.659822] ff60: 00000001 00004000 93adc200 81304f08 93b04541 0000000b 80085007 741d7ff4 [ 445.668019] ff80: 93b04540 93bfe000 00000036 8025716c 75742980 743caee0 01a152e0 00000036 [ 445.676214] ffa0: 80101204 80101000 75742980 743caee0 0000000b 80085007 741d7ff4 743cb004 [ 445.684410] ffc0: 75742980 743caee0 01a152e0 00000036 00000002 741d8064 741d81d4 76957ff8 [ 445.692605] ffe0: 743caf40 741d7fd4 743b88d1 76d2cfe8 80000030 0000000b 00000000 00000000 [ 445.700820] [<80550e20>] (pxp_device_ioctl) from [<80256c3c>] (do_vfs_ioctl+0x404/0x900) [ 445.708936] [<80256c3c>] (do_vfs_ioctl) from [<8025716c>] (ksys_ioctl+0x34/0x60) [ 445.716355] [<8025716c>] (ksys_ioctl) from [<80101000>] (ret_fast_syscall+0x0/0x54) [ 445.724023] Exception stack(0x93bfffa8 to 0x93bffff0) [ 445.729091] ffa0: 75742980 743caee0 0000000b 80085007 741d7ff4 743cb004 [ 445.737287] ffc0: 75742980 743caee0 01a152e0 00000036 00000002 741d8064 741d81d4 76957ff8 [ 445.745477] ffe0: 743caf40 741d7fd4 743b88d1 76d2cfe8 [ 445.750550] Code: e595100c e3a00000 e12fff34 eafffd39 (e594315c) [ 445.773509] ---[ end trace a4bb9353c99e0cef ]--- Signed-off-by: Robby Cai <[email protected]> Reviewed-by: G.n. Zhou <[email protected]> (cherry picked from commit 6543096) Signed-off-by: Andrey Zhizhikin <[email protected]>
Specify the clock rate and parent of i.MX8MQ/MM PCIe clocks. Signed-off-by: Richard Zhu <[email protected]> Reviewed-by: Jacky Bai <[email protected]> (cherry picked from commit 5c9865f4184ad9251d147126814a36e193226aae) (cherry picked from commit 768c144) Signed-off-by: Andrey Zhizhikin <[email protected]>
Since the parent clock setting had been done in dts node. Remove the codes from clock driver. Signed-off-by: Richard Zhu <[email protected]> Reviewed-by: Jacky Bai <[email protected]> (cherry picked from commit b4dd057204f0ba55e5ceea670b475204096e4f6c) (cherry picked from commit f619aad) Signed-off-by: Andrey Zhizhikin <[email protected]>
Correct one of the imx8mq_pcie1_ctrl_sels, from "sys2_pll_250m" to "sys2_pll_333m". Signed-off-by: Richard Zhu <[email protected]> Reviewed-by: Jacky Bai <[email protected]> (cherry picked from commit 6c34e907db3da694a63dbd44668189f769e686fe) (cherry picked from commit 6c24151) Signed-off-by: Andrey Zhizhikin <[email protected]>
… support or not HW board design may not support the L1.1 ASPM, although the L1.1 ASPM can be supported by the SOC chip. So, export one property to disable L1.1 ASPM supported or not. Signed-off-by: Richard Zhu <[email protected]> Reviewed-by: Jun Li <[email protected]> (cherry picked from commit 7bd2d56b72d33e223305aa2ef9046c0e38f225e6) (cherry picked from commit 439d54d) Signed-off-by: Andrey Zhizhikin <[email protected]>
Some HW boards might not support the L1.1 ASPM, although the L1.1 ASPM is supported by the SOC chip. So, export one property to disable L1.1 ASPM supported or not. Signed-off-by: Richard Zhu <[email protected]> Reviewed-by: Jun Li <[email protected]> (cherry picked from commit 4e42c418396d545a48a4eb47a04ce73a27b0415e) (cherry picked from commit 3edfbde) Signed-off-by: Andrey Zhizhikin <[email protected]>
…e used MIPI clock This patch replaced link-frequencies to express single/dual cameras case, which is introduced from 21c3114 MLK-23600-6 Update Basler camera link-frequencies to differentiate used MIPI clock Originally from Thies Moeller <[email protected]> With the fix for max-pixel-frequency for dual cameras basler camera + ov5640. For other sensor porting, could also use max-pixel-frequency property. Other properties might be optional. Signed-off-by: Robby Cai <[email protected]> Reviewed-by: G.n. Zhou <[email protected]> (cherry picked from commit 7f83103) Signed-off-by: Andrey Zhizhikin <[email protected]>
…up pcie phy Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY. In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design, the VREG_BYPASS bits of GPR registers should be cleared from default value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be turned on. Signed-off-by: Richard Zhu <[email protected]> Reviewed-by: Jun Li <[email protected]> (cherry picked from commit c14681471c737280d93d1e5f83221576caf352ee) (cherry picked from commit dc80c75) Signed-off-by: Andrey Zhizhikin <[email protected]>
…p pcie phy Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY. In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design, the VREG_BYPASS bits of GPR registers should be cleared from default value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be turned on. Signed-off-by: Richard Zhu <[email protected]> Reviewed-by: Jun Li <[email protected]> (cherry picked from commit d9f9d0c73d3965e6a7b130e2b762a8ff7d4f04a7) (cherry picked from commit 6430191) Signed-off-by: Andrey Zhizhikin <[email protected]>
Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY. In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design, the VREG_BYPASS bits of GPR registers should be cleared from default value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be turned on. Signed-off-by: Richard Zhu <[email protected]> Reviewed-by: Jun Li <[email protected]> (cherry picked from commit 94e84f467b688ce79eb3239f1516f6009b75a19b) (cherry picked from commit 9ffc904) Signed-off-by: Andrey Zhizhikin <[email protected]>
Disable the L1SS feature in default. Please remove this patch, if L1SS is required, and make sure that the HW supports L1SS. Signed-off-by: Richard Zhu <[email protected]> Reviewed-by: Jun Li <[email protected]> (cherry picked from commit 2843e1e62c991aab16150a56508d415fd43f3fbc) (cherry picked from commit 268df94) Signed-off-by: Andrey Zhizhikin <[email protected]>
Port the i2c over aux feature from 4.19.35 to the 5.4.x kernel. Add the the i2c read/write functions. The i2c features in the FW have been introduced in version 1.0.62. Signed-off-by: Julien Jayat <[email protected]> Signed-off-by: Oliver Brown <[email protected]> (cherry picked from commit b6181a1) Signed-off-by: Andrey Zhizhikin <[email protected]>
The power off need to be handled for the remove case so the clock enable counts are correct. Signed-off-by: Oliver Brown <[email protected]> (cherry picked from commit e8a7398) Signed-off-by: Andrey Zhizhikin <[email protected]>
The power off needs to be called in remove to keep the correct clock enable counts. Signed-off-by: Oliver Brown <[email protected]> (cherry picked from commit 6c855f4) Signed-off-by: Andrey Zhizhikin <[email protected]>
…e files MIPI1 and LVDS1 should be enabled in the HDMI configuration. Added DP configuration for MEK board. Signed-off-by: Oliver Brown <[email protected]> (cherry picked from commit cfdd6c6) Signed-off-by: Andrey Zhizhikin <[email protected]>
…ence Add explict memory barrier for the wdog unlock sequence. Suggested-by: Ye Li <[email protected]> Signed-off-by: Jacky Bai <[email protected]> Reviewed-by: Ye Li <[email protected]> (cherry picked from commit 59ec9bb) Signed-off-by: Andrey Zhizhikin <[email protected]>
Remove reserved memory for isp1 because now only use one isp0 for tuning tool. The reserved memory is only used for tuning tool, could be removed for normal operations. Signed-off-by: Robby Cai <[email protected]> Reviewed-by: G.n. Zhou <[email protected]> (cherry picked from commit 5f2220e) Signed-off-by: Andrey Zhizhikin <[email protected]>
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…format [ Upstream commit 06d213d ] For incoming SCO connection with transparent coding format, alt setting of CVSD is getting applied instead of Transparent. Before fix: < HCI Command: Accept Synchron.. (0x01|0x0029) plen 21 #2196 [hci0] 321.342548 Address: 1C:CC:D6:E2:EA:80 (Xiaomi Communications Co Ltd) Transmit bandwidth: 8000 Receive bandwidth: 8000 Max latency: 13 Setting: 0x0003 Input Coding: Linear Input Data Format: 1's complement Input Sample Size: 8-bit # of bits padding at MSB: 0 Air Coding Format: Transparent Data Retransmission effort: Optimize for link quality (0x02) Packet type: 0x003f HV1 may be used HV2 may be used HV3 may be used EV3 may be used EV4 may be used EV5 may be used > HCI Event: Command Status (0x0f) plen 4 #2197 [hci0] 321.343585 Accept Synchronous Connection Request (0x01|0x0029) ncmd 1 Status: Success (0x00) > HCI Event: Synchronous Connect Comp.. (0x2c) plen 17 #2198 [hci0] 321.351666 Status: Success (0x00) Handle: 257 Address: 1C:CC:D6:E2:EA:80 (Xiaomi Communications Co Ltd) Link type: eSCO (0x02) Transmission interval: 0x0c Retransmission window: 0x04 RX packet length: 60 TX packet length: 60 Air mode: Transparent (0x03) ........ > SCO Data RX: Handle 257 flags 0x00 dlen 48 #2336 [hci0] 321.383655 < SCO Data TX: Handle 257 flags 0x00 dlen 60 #2337 [hci0] 321.389558 > SCO Data RX: Handle 257 flags 0x00 dlen 48 #2338 [hci0] 321.393615 > SCO Data RX: Handle 257 flags 0x00 dlen 48 #2339 [hci0] 321.393618 > SCO Data RX: Handle 257 flags 0x00 dlen 48 #2340 [hci0] 321.393618 < SCO Data TX: Handle 257 flags 0x00 dlen 60 #2341 [hci0] 321.397070 > SCO Data RX: Handle 257 flags 0x00 dlen 48 #2342 [hci0] 321.403622 > SCO Data RX: Handle 257 flags 0x00 dlen 48 #2343 [hci0] 321.403625 > SCO Data RX: Handle 257 flags 0x00 dlen 48 #2344 [hci0] 321.403625 > SCO Data RX: Handle 257 flags 0x00 dlen 48 #2345 [hci0] 321.403625 < SCO Data TX: Handle 257 flags 0x00 dlen 60 #2346 [hci0] 321.404569 < SCO Data TX: Handle 257 flags 0x00 dlen 60 #2347 [hci0] 321.412091 > SCO Data RX: Handle 257 flags 0x00 dlen 48 #2348 [hci0] 321.413626 > SCO Data RX: Handle 257 flags 0x00 dlen 48 #2349 [hci0] 321.413630 > SCO Data RX: Handle 257 flags 0x00 dlen 48 #2350 [hci0] 321.413630 < SCO Data TX: Handle 257 flags 0x00 dlen 60 #2351 [hci0] 321.419674 After fix: < HCI Command: Accept Synchronou.. (0x01|0x0029) plen 21 Freescale#309 [hci0] 49.439693 Address: 1C:CC:D6:E2:EA:80 (Xiaomi Communications Co Ltd) Transmit bandwidth: 8000 Receive bandwidth: 8000 Max latency: 13 Setting: 0x0003 Input Coding: Linear Input Data Format: 1's complement Input Sample Size: 8-bit # of bits padding at MSB: 0 Air Coding Format: Transparent Data Retransmission effort: Optimize for link quality (0x02) Packet type: 0x003f HV1 may be used HV2 may be used HV3 may be used EV3 may be used EV4 may be used EV5 may be used > HCI Event: Command Status (0x0f) plen 4 Freescale#310 [hci0] 49.440308 Accept Synchronous Connection Request (0x01|0x0029) ncmd 1 Status: Success (0x00) > HCI Event: Synchronous Connect Complete (0x2c) plen 17 Freescale#311 [hci0] 49.449308 Status: Success (0x00) Handle: 257 Address: 1C:CC:D6:E2:EA:80 (Xiaomi Communications Co Ltd) Link type: eSCO (0x02) Transmission interval: 0x0c Retransmission window: 0x04 RX packet length: 60 TX packet length: 60 Air mode: Transparent (0x03) < SCO Data TX: Handle 257 flags 0x00 dlen 60 Freescale#312 [hci0] 49.450421 < SCO Data TX: Handle 257 flags 0x00 dlen 60 Freescale#313 [hci0] 49.457927 > HCI Event: Max Slots Change (0x1b) plen 3 Freescale#314 [hci0] 49.460345 Handle: 256 Max slots: 5 < SCO Data TX: Handle 257 flags 0x00 dlen 60 Freescale#315 [hci0] 49.465453 > SCO Data RX: Handle 257 flags 0x00 dlen 60 Freescale#316 [hci0] 49.470502 > SCO Data RX: Handle 257 flags 0x00 dlen 60 Freescale#317 [hci0] 49.470519 < SCO Data TX: Handle 257 flags 0x00 dlen 60 Freescale#318 [hci0] 49.472996 > SCO Data RX: Handle 257 flags 0x00 dlen 60 Freescale#319 [hci0] 49.480412 < SCO Data TX: Handle 257 flags 0x00 dlen 60 Freescale#320 [hci0] 49.480492 < SCO Data TX: Handle 257 flags 0x00 dlen 60 Freescale#321 [hci0] 49.487989 > SCO Data RX: Handle 257 flags 0x00 dlen 60 Freescale#322 [hci0] 49.490303 < SCO Data TX: Handle 257 flags 0x00 dlen 60 Freescale#323 [hci0] 49.495496 > SCO Data RX: Handle 257 flags 0x00 dlen 60 Freescale#324 [hci0] 49.500304 > SCO Data RX: Handle 257 flags 0x00 dlen 60 Freescale#325 [hci0] 49.500311 Signed-off-by: Kiran K <[email protected]> Signed-off-by: Lokendra Singh <[email protected]> Signed-off-by: Marcel Holtmann <[email protected]> Signed-off-by: Sasha Levin <[email protected]>
zandrey
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Jul 20, 2021
…format [ Upstream commit 06d213d ] For incoming SCO connection with transparent coding format, alt setting of CVSD is getting applied instead of Transparent. Before fix: < HCI Command: Accept Synchron.. (0x01|0x0029) plen 21 #2196 [hci0] 321.342548 Address: 1C:CC:D6:E2:EA:80 (Xiaomi Communications Co Ltd) Transmit bandwidth: 8000 Receive bandwidth: 8000 Max latency: 13 Setting: 0x0003 Input Coding: Linear Input Data Format: 1's complement Input Sample Size: 8-bit # of bits padding at MSB: 0 Air Coding Format: Transparent Data Retransmission effort: Optimize for link quality (0x02) Packet type: 0x003f HV1 may be used HV2 may be used HV3 may be used EV3 may be used EV4 may be used EV5 may be used > HCI Event: Command Status (0x0f) plen 4 #2197 [hci0] 321.343585 Accept Synchronous Connection Request (0x01|0x0029) ncmd 1 Status: Success (0x00) > HCI Event: Synchronous Connect Comp.. (0x2c) plen 17 #2198 [hci0] 321.351666 Status: Success (0x00) Handle: 257 Address: 1C:CC:D6:E2:EA:80 (Xiaomi Communications Co Ltd) Link type: eSCO (0x02) Transmission interval: 0x0c Retransmission window: 0x04 RX packet length: 60 TX packet length: 60 Air mode: Transparent (0x03) ........ > SCO Data RX: Handle 257 flags 0x00 dlen 48 #2336 [hci0] 321.383655 < SCO Data TX: Handle 257 flags 0x00 dlen 60 #2337 [hci0] 321.389558 > SCO Data RX: Handle 257 flags 0x00 dlen 48 #2338 [hci0] 321.393615 > SCO Data RX: Handle 257 flags 0x00 dlen 48 #2339 [hci0] 321.393618 > SCO Data RX: Handle 257 flags 0x00 dlen 48 #2340 [hci0] 321.393618 < SCO Data TX: Handle 257 flags 0x00 dlen 60 #2341 [hci0] 321.397070 > SCO Data RX: Handle 257 flags 0x00 dlen 48 #2342 [hci0] 321.403622 > SCO Data RX: Handle 257 flags 0x00 dlen 48 #2343 [hci0] 321.403625 > SCO Data RX: Handle 257 flags 0x00 dlen 48 #2344 [hci0] 321.403625 > SCO Data RX: Handle 257 flags 0x00 dlen 48 #2345 [hci0] 321.403625 < SCO Data TX: Handle 257 flags 0x00 dlen 60 #2346 [hci0] 321.404569 < SCO Data TX: Handle 257 flags 0x00 dlen 60 #2347 [hci0] 321.412091 > SCO Data RX: Handle 257 flags 0x00 dlen 48 #2348 [hci0] 321.413626 > SCO Data RX: Handle 257 flags 0x00 dlen 48 #2349 [hci0] 321.413630 > SCO Data RX: Handle 257 flags 0x00 dlen 48 #2350 [hci0] 321.413630 < SCO Data TX: Handle 257 flags 0x00 dlen 60 #2351 [hci0] 321.419674 After fix: < HCI Command: Accept Synchronou.. (0x01|0x0029) plen 21 Freescale#309 [hci0] 49.439693 Address: 1C:CC:D6:E2:EA:80 (Xiaomi Communications Co Ltd) Transmit bandwidth: 8000 Receive bandwidth: 8000 Max latency: 13 Setting: 0x0003 Input Coding: Linear Input Data Format: 1's complement Input Sample Size: 8-bit # of bits padding at MSB: 0 Air Coding Format: Transparent Data Retransmission effort: Optimize for link quality (0x02) Packet type: 0x003f HV1 may be used HV2 may be used HV3 may be used EV3 may be used EV4 may be used EV5 may be used > HCI Event: Command Status (0x0f) plen 4 Freescale#310 [hci0] 49.440308 Accept Synchronous Connection Request (0x01|0x0029) ncmd 1 Status: Success (0x00) > HCI Event: Synchronous Connect Complete (0x2c) plen 17 Freescale#311 [hci0] 49.449308 Status: Success (0x00) Handle: 257 Address: 1C:CC:D6:E2:EA:80 (Xiaomi Communications Co Ltd) Link type: eSCO (0x02) Transmission interval: 0x0c Retransmission window: 0x04 RX packet length: 60 TX packet length: 60 Air mode: Transparent (0x03) < SCO Data TX: Handle 257 flags 0x00 dlen 60 Freescale#312 [hci0] 49.450421 < SCO Data TX: Handle 257 flags 0x00 dlen 60 Freescale#313 [hci0] 49.457927 > HCI Event: Max Slots Change (0x1b) plen 3 Freescale#314 [hci0] 49.460345 Handle: 256 Max slots: 5 < SCO Data TX: Handle 257 flags 0x00 dlen 60 Freescale#315 [hci0] 49.465453 > SCO Data RX: Handle 257 flags 0x00 dlen 60 Freescale#316 [hci0] 49.470502 > SCO Data RX: Handle 257 flags 0x00 dlen 60 Freescale#317 [hci0] 49.470519 < SCO Data TX: Handle 257 flags 0x00 dlen 60 Freescale#318 [hci0] 49.472996 > SCO Data RX: Handle 257 flags 0x00 dlen 60 Freescale#319 [hci0] 49.480412 < SCO Data TX: Handle 257 flags 0x00 dlen 60 Freescale#320 [hci0] 49.480492 < SCO Data TX: Handle 257 flags 0x00 dlen 60 Freescale#321 [hci0] 49.487989 > SCO Data RX: Handle 257 flags 0x00 dlen 60 Freescale#322 [hci0] 49.490303 < SCO Data TX: Handle 257 flags 0x00 dlen 60 Freescale#323 [hci0] 49.495496 > SCO Data RX: Handle 257 flags 0x00 dlen 60 Freescale#324 [hci0] 49.500304 > SCO Data RX: Handle 257 flags 0x00 dlen 60 Freescale#325 [hci0] 49.500311 Signed-off-by: Kiran K <[email protected]> Signed-off-by: Lokendra Singh <[email protected]> Signed-off-by: Marcel Holtmann <[email protected]> Signed-off-by: Sasha Levin <[email protected]>
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Apr 10, 2024
[ Upstream commit a51cd6b ] In case when is64 == 1 in emit(A64_REV32(is64, dst, dst), ctx) the generated insn reverses byte order for both high and low 32-bit words, resuling in an incorrect swap as indicated by the jit test: [ 9757.262607] test_bpf: #312 BSWAP 16: 0x0123456789abcdef -> 0xefcd jited:1 8 PASS [ 9757.264435] test_bpf: #313 BSWAP 32: 0x0123456789abcdef -> 0xefcdab89 jited:1 ret 1460850314 != -271733879 (0x5712ce8a != 0xefcdab89)FAIL (1 times) [ 9757.266260] test_bpf: #314 BSWAP 64: 0x0123456789abcdef -> 0x67452301 jited:1 8 PASS [ 9757.268000] test_bpf: #315 BSWAP 64: 0x0123456789abcdef >> 32 -> 0xefcdab89 jited:1 8 PASS [ 9757.269686] test_bpf: #316 BSWAP 16: 0xfedcba9876543210 -> 0x1032 jited:1 8 PASS [ 9757.271380] test_bpf: #317 BSWAP 32: 0xfedcba9876543210 -> 0x10325476 jited:1 ret -1460850316 != 271733878 (0xa8ed3174 != 0x10325476)FAIL (1 times) [ 9757.273022] test_bpf: #318 BSWAP 64: 0xfedcba9876543210 -> 0x98badcfe jited:1 7 PASS [ 9757.274721] test_bpf: #319 BSWAP 64: 0xfedcba9876543210 >> 32 -> 0x10325476 jited:1 9 PASS Fix this by forcing 32bit variant of rev32. Fixes: 1104247 ("bpf, arm64: Support unconditional bswap") Signed-off-by: Artem Savkov <[email protected]> Tested-by: Puranjay Mohan <[email protected]> Acked-by: Puranjay Mohan <[email protected]> Acked-by: Xu Kuohai <[email protected]> Message-ID: <[email protected]> Signed-off-by: Alexei Starovoitov <[email protected]> Signed-off-by: Sasha Levin <[email protected]>
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Cherry-pick NXP patches, that are integrated as a part of
rel_imx_5.4.70_2.3.2tag.Total 48 patches are integrated. Corresponding commit SHAs in NXP tree are recorded in cherry-picked versions.
Kernel has been built for both aarch64 (
imx_v8_defconfig) and arm32 (imx_v7_defconfig).-- andrey