GSG IBERT
###Intro
This project set intends to show the availability of certain transceivers on the boards, using Xilinx IBERT tools.
Get the transceivers on the board verified.
Demo runs directly with JTAG downloading in Xilinx Vivado HW Manager.
Boot image with FSBL board clock setup may be necessary, depending on the design.
###Project List
| Board | Project |
|---|---|
| ONetSwitch20 | N/A |
| ONetSwitch30 | ons30-gsg-2-gt_ibert |
| ONetSwitch45 | ons45-gsg-2-gt_ibert |
###Pre-Built Images
- For quick start demo.
| File | ONetSwitch20 | ONetSwitch30 | ONetSwitch45 |
|---|---|---|---|
| boot.bin | N/A |
Download |
N/A |
| system.bit | N/A |
Download |
Download |
###Target
- Verify the quality of the signal from/to each transceiver by sending PRBS.
- Check the PLL status and link status for transceivers.
- Check the eye-diagrams.
###Block Diagram
-
ONetSwitch30
-
ONetSwitch45
###Design Outline
- Follow the steps described in Xilinx PG132 to generate the GTX Quad according to the board hardware specifications. Notice to use the correct refclk for the Quad.
- ONS30, 6Gbps(150MHz) or 5Gbps(125MHz)
- ONS45, 10GBase-R 10.3125Gbps(156.25MHz)
- Generate the final bitfile.
- (For ONS30) Download the boot.bin for refclk configuration.
###Demo
- Setup the demo environment by interconnecting the GTX.
- (For ONS30) Any 2 pairs from J5, J6, J7 and J8 by using 2 SATA cables.
- (For ONS45) Any 2 pairs from the 4 SFP+ by using 2 SFP+ twinax cables.
- (For ONS30) For the bootloader programming the AD9516-3 clock-gen, power on the board with boot.bin in TF card.
- Program the FPGA using the system.bit above in Vivado hardware manager, follow the guide to create links among the transceivers.
- Check the link status and bit errors. Should be without any BER. You can manually use error injection to check.
- Optional eye-diagram scanning can be performed.
###Vivado2013.4
In Vivado2013.4, for ONS30, the template of IBERT IP for XC7Z030-2SBG485 is incorrect when generating the wrapper for example design. Please refer to the reference top.v for the working implementation. Or you can directly build from the ons30-gsg-2-gt_ibert project rather than follow the IP/example design generation.