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CVE-2017-5715 AArch64 #2072
CVE-2017-5715 AArch64 #2072
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There's some strace build error for the Hikey auto builder:
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Nice and clean, IMO! I have only two minor comments. Anyway:
Reviewed-by: Jerome Forissier <[email protected]>
Tested-by: Jerome Forissier <[email protected]> (HiKey960)
(Note that HiKey960 has 4x Cortex-A73 and 4x Cortex-A53 so it is a good test for this code).
core/arch/arm/kernel/thread_a64.S
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@@ -507,6 +529,117 @@ el0_serror_a32: | |||
b el0_serror_a32 | |||
check_vector_size el0_serror_a32 | |||
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#if defined(CFG_CORE_WORKAROUND_SPECTRE_BP_SEC) | |||
.macro apply_workaround |
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apply_workaround
is a bit too vague IMO. s/apply_workaround/ic_iallu_isb/
? Or if you prefer s/apply_workaround/icache_invalidate/
?
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ARM-TF is mentioning a low overhead SMC interface for to invalidate the branch predictor, maybe that could be used later.
I guess s/apply_workaround/invalidate_branch_predictor/
would be good enough.
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Sounds good
core/arch/arm/kernel/thread_a64.S
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@@ -379,31 +379,31 @@ END_FUNC thread_unwind_user_mode | |||
.endm | |||
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.section .text.thread_vect_table | |||
.align 11 | |||
.align 11, 0 |
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How could we make it more obvious that 0 is an invalid instruction? #define INV_INSN 0
maybe?
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Commit subject: s/arm32/arm64
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I'll fix
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Comments addressed, tags applied. |
Moves MIDR definitions from arm32.h to arm.h Reviewed-by: Jerome Forissier <[email protected]> Signed-off-by: Jens Wiklander <[email protected]>
Renames the labels in the exception vector to use consistent lower case names. Reviewed-by: Jerome Forissier <[email protected]> Signed-off-by: Jens Wiklander <[email protected]>
Pads exception vector with an illegal instruction to improve robustness. Reviewed-by: Jerome Forissier <[email protected]> Signed-off-by: Jens Wiklander <[email protected]>
With CFG_CORE_UNMAP_CORE_AT_EL0=y the exception vector is updated to use the minimal kernel mapping during user space execution. With this patch vbar is updated relative to previous value in vbar to allow different exception vectors for different cpu types. Reviewed-by: Jerome Forissier <[email protected]> Signed-off-by: Jens Wiklander <[email protected]>
If build with CFG_CORE_WORKAROUND_SPECTRE_BP_SEC=y invalidate branch predictor on all secure world exceptions originating in secure EL0 (secure user space). Fixes CVE-2017-5715 Reviewed-by: Jerome Forissier <[email protected]> Tested-by: Jerome Forissier <[email protected]> (HiKey960) Signed-off-by: Jens Wiklander <[email protected]>
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Rebased on master |
- The Spectre v1 investigation found no vulnerability - Mention the recent arm64 branch invalidation update included in OP-TEE 3.1.0 (OP-TEE/optee_os#2229). The previous security fix (OP-TEE/optee_os#2072) was not effective as a mitigation against Spectre v2. Signed-off-by: Jerome Forissier <[email protected]>
- The Spectre v1 investigation found no vulnerability - Mention the recent arm64 branch invalidation update included in OP-TEE 3.1.0 (OP-TEE/optee_os#2229). The previous security fix (OP-TEE/optee_os#2072) was not effective as a mitigation against Spectre v2. Signed-off-by: Jerome Forissier <[email protected]> Acked-by: Joakim Bech <[email protected]>
- The Spectre v1 investigation found no vulnerability - Mention the recent arm64 branch invalidation update included in OP-TEE 3.1.0 (OP-TEE/optee_os#2229). The previous security fix (OP-TEE/optee_os#2072) was not effective as a mitigation against Spectre v2. Signed-off-by: Jerome Forissier <[email protected]> Acked-by: Joakim Bech <[email protected]>
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