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CVE-2017-5715 AArch64 #2072

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merged 5 commits into from
Jan 16, 2018
Merged

CVE-2017-5715 AArch64 #2072

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536ff1b
core: arm.h: move midr definitions
jenswi-linaro Jan 15, 2018
e7e589c
core: thread_a64.S: cleanup vector entries
jenswi-linaro Jan 15, 2018
37655b5
core: arm64: pad vector with illegal instruction
jenswi-linaro Jan 15, 2018
0ea869b
core: arm64: thread: update vector relative to vbar
jenswi-linaro Jan 15, 2018
2f93d96
core: arm64.S: spectre workaround
jenswi-linaro Jan 15, 2018
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3 changes: 3 additions & 0 deletions core/arch/arm/arm.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -36,6 +36,9 @@ endif
# See also https://developer.arm.com/-/media/Files/pdf/Cache_Speculation_Side-channels.pdf
# Variant 2
CFG_CORE_WORKAROUND_SPECTRE_BP ?= y
# Same as CFG_CORE_WORKAROUND_SPECTRE_BP but targeting exceptions from
# secure EL0 instead of non-secure world.
CFG_CORE_WORKAROUND_SPECTRE_BP_SEC ?= $(CFG_CORE_WORKAROUND_SPECTRE_BP)

CFG_CORE_RWDATA_NOEXEC ?= y
CFG_CORE_RODATA_NOEXEC ?= n
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20 changes: 19 additions & 1 deletion core/arch/arm/include/arm.h
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Expand Up @@ -7,11 +7,29 @@

#include <util.h>

/* MIDR definitions */
#define MIDR_PRIMARY_PART_NUM_SHIFT 4
#define MIDR_PRIMARY_PART_NUM_WIDTH 12

#define MIDR_IMPLEMENTER_SHIFT 24
#define MIDR_IMPLEMENTER_WIDTH 8
#define MIDR_IMPLEMENTER_ARM 0x41

#define CORTEX_A7_PART_NUM 0xC07
#define CORTEX_A8_PART_NUM 0xC08
#define CORTEX_A9_PART_NUM 0xC09
#define CORTEX_A15_PART_NUM 0xC0F
#define CORTEX_A17_PART_NUM 0xC0E
#define CORTEX_A57_PART_NUM 0xD07
#define CORTEX_A72_PART_NUM 0xD08
#define CORTEX_A73_PART_NUM 0xD09
#define CORTEX_A75_PART_NUM 0xD0A

/* MPIDR definitions */
#define MPIDR_CPU_MASK 0xff
#define MPIDR_CLUSTER_SHIFT 8
#define MPIDR_CLUSTER_MASK (0xff << MPIDR_CLUSTER_SHIFT)


/* CLIDR definitions */
#define CLIDR_LOUIS_SHIFT 21
#define CLIDR_LOC_SHIFT 24
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17 changes: 0 additions & 17 deletions core/arch/arm/include/arm32.h
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Expand Up @@ -34,23 +34,6 @@
#include <stdint.h>
#include <util.h>

#define CORTEX_A7_PART_NUM 0xC07
#define CORTEX_A8_PART_NUM 0xC08
#define CORTEX_A9_PART_NUM 0xC09
#define CORTEX_A15_PART_NUM 0xC0F
#define CORTEX_A17_PART_NUM 0xC0E
#define CORTEX_A57_PART_NUM 0xD07
#define CORTEX_A72_PART_NUM 0xD08
#define CORTEX_A73_PART_NUM 0xD09
#define CORTEX_A75_PART_NUM 0xD0A

#define MIDR_PRIMARY_PART_NUM_SHIFT 4
#define MIDR_PRIMARY_PART_NUM_WIDTH 12

#define MIDR_IMPLEMENTER_SHIFT 24
#define MIDR_IMPLEMENTER_WIDTH 8
#define MIDR_IMPLEMENTER_ARM 0x41

#define CPSR_MODE_MASK ARM32_CPSR_MODE_MASK
#define CPSR_MODE_USR ARM32_CPSR_MODE_USR
#define CPSR_MODE_FIQ ARM32_CPSR_MODE_FIQ
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