Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

fix(csr): add support Non-registers interrupt pending to diff xip #3572

Merged
merged 4 commits into from
Oct 2, 2024
Merged

fix(csr): add support Non-registers interrupt pending to diff xip #3572

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
4 commits
Select commit Hold shift + click to select a range
9a3d8eb
fix(csr, difftest): remove skip csr and add diffevent to csr
sinceforYy Sep 13, 2024
9d99177
submodule(difftest): bump difftest
sinceforYy Sep 30, 2024
fb09585
submodule(ready-to-run): bump ready-to-run
sinceforYy Sep 30, 2024
e624459
fix(CSR): fix `platformIRPVstipChange` assignment
Tang-Haojin Oct 1, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion difftest
Open in desktop
Submodule difftest updated 15 files
+3 −3 .github/workflows/main.yml
+1 −0 README.md
+4 −4 config/config.h
+5 −3 palladium.mk
+6 −5 src/main/scala/Batch.scala
+11 −0 src/main/scala/Bundles.scala
+34 −31 src/main/scala/DPIC.scala
+5 −0 src/main/scala/Difftest.scala
+11 −14 src/main/scala/Gateway.scala
+5 −2 src/test/csrc/common/perf.cpp
+2 −0 src/test/csrc/common/perf.h
+22 −5 src/test/csrc/difftest/difftest.cpp
+3 −1 src/test/csrc/difftest/difftest.h
+19 −1 src/test/csrc/difftest/refproxy.h
+2 −1 src/test/scala/DifftestTop.scala
2 changes: 1 addition & 1 deletion ready-to-run
Open in desktop
Submodule ready-to-run updated 3 files
+ − riscv64-nemu-interpreter-dual-so
+ − riscv64-nemu-interpreter-so
+ − riscv64-spike-so
40 changes: 35 additions & 5 deletions src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -774,10 +774,7 @@ class NewCSR(implicit val p: Parameters) extends Module
(addr >= CSRs.mcycle.U) && (addr <= CSRs.mhpmcounter31.U) ||
(addr === mcountinhibit.addr.U) ||
(addr >= CSRs.cycle.U) && (addr <= CSRs.hpmcounter31.U) ||
(addr === CSRs.mip.U) || (addr === CSRs.sip.U) || (addr === CSRs.vsip.U) ||
(addr === CSRs.hip.U) || (addr === CSRs.mvip.U) || (addr === CSRs.hvip.U) ||
Cat(aiaSkipCSRs.map(_.addr.U === addr)).orR ||
(addr === CSRs.stimecmp.U)
Cat(aiaSkipCSRs.map(_.addr.U === addr)).orR
)

// flush
Expand Down Expand Up @@ -1286,7 +1283,7 @@ class NewCSR(implicit val p: Parameters) extends Module
diffCSRState.mcause := mcause.rdata.asUInt
diffCSRState.scause := scause.rdata.asUInt
diffCSRState.satp := satp.rdata.asUInt
diffCSRState.mip := mip.regOut.asUInt
diffCSRState.mip := mip.rdata.asUInt
diffCSRState.mie := mie.rdata.asUInt
diffCSRState.mscratch := mscratch.rdata.asUInt
diffCSRState.sscratch := sscratch.rdata.asUInt
Expand Down Expand Up @@ -1342,6 +1339,39 @@ class NewCSR(implicit val p: Parameters) extends Module
diffHCSRState.vsatp := vsatp.rdata.asUInt
diffHCSRState.vsscratch := vsscratch.rdata.asUInt

val platformIRPMeipChange = !platformIRP.MEIP && RegNext(platformIRP.MEIP) ||
platformIRP.MEIP && !RegNext(platformIRP.MEIP) ||
!fromAIA.meip && RegNext(fromAIA.meip) ||
fromAIA.meip && !RegNext(fromAIA.meip)
val platformIRPMtipChange = !platformIRP.MTIP && RegNext(platformIRP.MTIP) || platformIRP.MTIP && !RegNext(platformIRP.MTIP)
val platformIRPMsipChange = !platformIRP.MSIP && RegNext(platformIRP.MSIP) || platformIRP.MSIP && !RegNext(platformIRP.MSIP)
val platformIRPSeipChange = !platformIRP.SEIP && RegNext(platformIRP.SEIP) ||
platformIRP.SEIP && !RegNext(platformIRP.SEIP) ||
!fromAIA.seip && RegNext(fromAIA.seip) ||
fromAIA.seip && !RegNext(fromAIA.seip)
val platformIRPStipChange = !sstcIRGen.o.STIP && RegNext(sstcIRGen.o.STIP) || sstcIRGen.o.STIP && !RegNext(sstcIRGen.o.STIP)
val platformIRPVseipChange = !platformIRP.VSEIP && RegNext(platformIRP.VSEIP) ||
platformIRP.VSEIP && !RegNext(platformIRP.VSEIP) ||
!hgeip.rdata.asUInt(hstatus.regOut.VGEIN.asUInt) && RegNext(hgeip.rdata.asUInt(hstatus.regOut.VGEIN.asUInt)) ||
hgeip.rdata.asUInt(hstatus.regOut.VGEIN.asUInt) && !RegNext(hgeip.rdata.asUInt(hstatus.regOut.VGEIN.asUInt))
val platformIRPVstipChange = !sstcIRGen.o.VSTIP && RegNext(sstcIRGen.o.VSTIP) || sstcIRGen.o.VSTIP && !RegNext(sstcIRGen.o.VSTIP)
val lcofiReqChange = !lcofiReq && RegNext(lcofiReq) || lcofiReq && !RegNext(lcofiReq)

val diffNonRegInterruptPendingEvent = DifftestModule(new DiffNonRegInterruptPendingEvent)
diffNonRegInterruptPendingEvent.coreid := hartId
diffNonRegInterruptPendingEvent.valid := platformIRPMeipChange || platformIRPMtipChange || platformIRPMsipChange ||
platformIRPSeipChange || platformIRPStipChange ||
platformIRPVseipChange || platformIRPVstipChange ||
lcofiReqChange
diffNonRegInterruptPendingEvent.platformIRPMeip := platformIRP.MEIP || fromAIA.meip
diffNonRegInterruptPendingEvent.platformIRPMtip := platformIRP.MTIP
diffNonRegInterruptPendingEvent.platformIRPMsip := platformIRP.MSIP
diffNonRegInterruptPendingEvent.platformIRPSeip := platformIRP.SEIP || fromAIA.seip
diffNonRegInterruptPendingEvent.platformIRPStip := sstcIRGen.o.STIP
diffNonRegInterruptPendingEvent.platformIRPVseip := platformIRP.VSEIP || hgeip.rdata.asUInt(hstatus.regOut.VGEIN.asUInt)
diffNonRegInterruptPendingEvent.platformIRPVstip := sstcIRGen.o.VSTIP
diffNonRegInterruptPendingEvent.localCounterOverflowInterruptReq := lcofiReq

}
}

Expand Down
Loading