fix(csr): add support Non-registers interrupt pending to diff xip #3572
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Remove skip csr for xip, menvcfg, henvcfg to diff Add diffevent to support no reg interrupt pending
* difftest commit: fbd72a2e718dc37b924bc3e7239d86f8452bd428 including: * fix(config): allow 8GB memory as default for unknown CPUs (OpenXiangShan#466) * fix(csr): add support non register interrupt pending (OpenXiangShan#465) * fix(csr): fix struct non-reg interrupt pending to order (OpenXiangShan#469) * palladium: Build DPILIB_EMU shared library as separated targets (OpenXiangShan#468) * Difftest: Use file API compatible with with Java8 (OpenXiangShan#467) * Batch: pack Batch param to facilitate migration between DPIC/PCIe (OpenXiangShan#474)
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This PR add support Non-register interrupt pending which come from platform.
Interrupts that cannot be generated by NEMU can be obtained through XiangShan ->Difftest ->NEMU.
Remove skip xip, xenvcfg to diff xip, xenvcfg.
Bump difftest and ready-to-run.