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fix(csr): add support Non-registers interrupt pending to diff xip #3572

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Commits on Sep 28, 2024

  1. fix(csr, difftest): remove skip csr and add diffevent to csr

    Remove skip csr for xip, menvcfg, henvcfg to diff
    Add diffevent to support no reg interrupt pending
    sinceforYy committed Sep 28, 2024
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  2. submodule(difftest): bump difftest

    * difftest commit: fbd72a2e718dc37b924bc3e7239d86f8452bd428
    
    including:
    * fix(config): allow 8GB memory as default for unknown CPUs (OpenXiangShan#466)
    * fix(csr): add support non register interrupt pending (OpenXiangShan#465)
    * fix(csr): fix struct non-reg interrupt pending to order (OpenXiangShan#469)
    * palladium: Build DPILIB_EMU shared library as separated targets (OpenXiangShan#468)
    * Difftest: Use file API compatible with with Java8 (OpenXiangShan#467)
    * Batch: pack Batch param to facilitate migration between DPIC/PCIe (OpenXiangShan#474)
    sinceforYy committed Sep 28, 2024
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