backend,roq: RegNext isEmpty and block commits when exceptions for better timing #467
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roq: optimize commit timing and block commits when exceptions occur
Lemover
approved these changes
Jan 21, 2021
sinceforYy
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Sep 27, 2024
* difftest commit: ca4fce1867b23ebd9af27a4fa8627d2787bbee3a including: * fix(config): allow 8GB memory as default for unknown CPUs (OpenXiangShan#466) * fix(csr): add support non register interrupt pending (OpenXiangShan#465) * fix(csr): fix struct non-reg interrupt pending to order (OpenXiangShan#469) * palladium: Build DPILIB_EMU shared library as separated targets (OpenXiangShan#468) * Difftest: Use file API compatible with with Java8 (OpenXiangShan#467) * Batch: pack Batch param to facilitate migration between DPIC/PCIe (OpenXiangShan#474) * fix(cmo): add cmo inval event * feat(mem): add optional ref func ref_memcpy_init (OpenXiangShan#475) * Merge pull request OpenXiangShan#476 from OpenXiangShan/fix-cmo
sinceforYy
added a commit
to sinceforYy/XiangShan
that referenced
this pull request
Sep 28, 2024
* difftest commit: ca4fce1867b23ebd9af27a4fa8627d2787bbee3a including: * fix(config): allow 8GB memory as default for unknown CPUs (OpenXiangShan#466) * fix(csr): add support non register interrupt pending (OpenXiangShan#465) * fix(csr): fix struct non-reg interrupt pending to order (OpenXiangShan#469) * palladium: Build DPILIB_EMU shared library as separated targets (OpenXiangShan#468) * Difftest: Use file API compatible with with Java8 (OpenXiangShan#467) * Batch: pack Batch param to facilitate migration between DPIC/PCIe (OpenXiangShan#474) * fix(cmo): add cmo inval event * feat(mem): add optional ref func ref_memcpy_init (OpenXiangShan#475) * Merge pull request OpenXiangShan#476 from OpenXiangShan/fix-cmo
sinceforYy
added a commit
to sinceforYy/XiangShan
that referenced
this pull request
Sep 28, 2024
* difftest commit: fbd72a2e718dc37b924bc3e7239d86f8452bd428 including: * fix(config): allow 8GB memory as default for unknown CPUs (OpenXiangShan#466) * fix(csr): add support non register interrupt pending (OpenXiangShan#465) * fix(csr): fix struct non-reg interrupt pending to order (OpenXiangShan#469) * palladium: Build DPILIB_EMU shared library as separated targets (OpenXiangShan#468) * Difftest: Use file API compatible with with Java8 (OpenXiangShan#467) * Batch: pack Batch param to facilitate migration between DPIC/PCIe (OpenXiangShan#474)
sinceforYy
added a commit
to sinceforYy/XiangShan
that referenced
this pull request
Sep 30, 2024
* difftest commit: fbd72a2e718dc37b924bc3e7239d86f8452bd428 including: * fix(config): allow 8GB memory as default for unknown CPUs (OpenXiangShan#466) * fix(csr): add support non register interrupt pending (OpenXiangShan#465) * fix(csr): fix struct non-reg interrupt pending to order (OpenXiangShan#469) * palladium: Build DPILIB_EMU shared library as separated targets (OpenXiangShan#468) * Difftest: Use file API compatible with with Java8 (OpenXiangShan#467) * Batch: pack Batch param to facilitate migration between DPIC/PCIe (OpenXiangShan#474)
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