Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

SRAMTemplate: support --infer-rw --repl-seq-mem #474

Merged
merged 2 commits into from
Jan 22, 2021

Conversation

poemonsense
Copy link
Member

No description provided.

@poemonsense poemonsense merged commit a99217c into master Jan 22, 2021
@poemonsense poemonsense deleted the fix-sram-template branch January 22, 2021 07:35
sinceforYy added a commit to sinceforYy/XiangShan that referenced this pull request Sep 27, 2024
* difftest commit: ca4fce1867b23ebd9af27a4fa8627d2787bbee3a

including:
* fix(config): allow 8GB memory as default for unknown CPUs (OpenXiangShan#466)
* fix(csr): add support non register interrupt pending (OpenXiangShan#465)
* fix(csr): fix struct non-reg interrupt pending to order (OpenXiangShan#469)
* palladium: Build DPILIB_EMU shared library as separated targets (OpenXiangShan#468)
* Difftest: Use file API compatible with with Java8 (OpenXiangShan#467)
* Batch: pack Batch param to facilitate migration between DPIC/PCIe
  (OpenXiangShan#474)
* fix(cmo): add cmo inval event
* feat(mem): add optional ref func ref_memcpy_init (OpenXiangShan#475)
* Merge pull request OpenXiangShan#476 from OpenXiangShan/fix-cmo
sinceforYy added a commit to sinceforYy/XiangShan that referenced this pull request Sep 28, 2024
* difftest commit: ca4fce1867b23ebd9af27a4fa8627d2787bbee3a

including:
* fix(config): allow 8GB memory as default for unknown CPUs (OpenXiangShan#466)
* fix(csr): add support non register interrupt pending (OpenXiangShan#465)
* fix(csr): fix struct non-reg interrupt pending to order (OpenXiangShan#469)
* palladium: Build DPILIB_EMU shared library as separated targets (OpenXiangShan#468)
* Difftest: Use file API compatible with with Java8 (OpenXiangShan#467)
* Batch: pack Batch param to facilitate migration between DPIC/PCIe
  (OpenXiangShan#474)
* fix(cmo): add cmo inval event
* feat(mem): add optional ref func ref_memcpy_init (OpenXiangShan#475)
* Merge pull request OpenXiangShan#476 from OpenXiangShan/fix-cmo
sinceforYy added a commit to sinceforYy/XiangShan that referenced this pull request Sep 28, 2024
* difftest commit: fbd72a2e718dc37b924bc3e7239d86f8452bd428

including:
* fix(config): allow 8GB memory as default for unknown CPUs (OpenXiangShan#466)
* fix(csr): add support non register interrupt pending (OpenXiangShan#465)
* fix(csr): fix struct non-reg interrupt pending to order (OpenXiangShan#469)
* palladium: Build DPILIB_EMU shared library as separated targets (OpenXiangShan#468)
* Difftest: Use file API compatible with with Java8 (OpenXiangShan#467)
* Batch: pack Batch param to facilitate migration between DPIC/PCIe (OpenXiangShan#474)
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

3 participants