Use transceiver clocks in FINC/FDEC tests #538
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martijnbastiaan
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This allows us to directly use the GTH reference clock in logic, by selecting TXPLLREFCLK_DIV1, and do the FincFdec test on all nodes without extra cables.
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The HITL test
fincFdecTestsis no longer run when a branch is pushed, so I've added a debug.json to explicitly test it. The result of that test can be seen here.The main goal of this PR is to enable us to run the FINC/FDEC tests on all FPGAs in the demo rig. To do this, we need access to the external clock, which is connected to
SMA_MGT_REFCLK_Cand which can only be used by the transceivers. We therefore modifiedgthCoreto allow access to this clock before it goes through the internal CPLL (see this diagram in the GTH Transceiver user guide.To select
TXPLLREFCLK_DIV1asTXOUTCLK, we need a different ratio between the reference clock and 125 MHz TX clock. We therefore changed the external clock from 200 MHz to 250 MHz for all bittide instances. Note that this does not interfere with internals of any bittide instance, it only changes the reference clock of the transceivers.