[Issue-133] simcompare calculate signaltowidth instead of manual input

lib/src/utilities/simcompare.dart

@@ -144,19 +144,19 @@ abstract class SimCompare {
 
   /// Executes [vectors] against the Icarus Verilog simulator.
   static bool iverilogVector(
+    Module module,
     String generatedVerilog,
     String topModule,
     List<Vector> vectors, {
     bool dontDeleteTmpFiles = false,
     bool dumpWaves = false,
-    Map<String, int> signalToWidthMap = const {},
     List<String> iverilogExtraArgs = const [],
     bool allowWarnings = false,
   }) {
     String signalDeclaration(String signalName) {
-      if (signalToWidthMap.containsKey(signalName)) {
-        final width = signalToWidthMap[signalName]!;
-        return '[${width - 1}:0] $signalName';
+      final signals = module.signals.firstWhere((e) => e.name == signalName);
+      if (signals.width != 1) {
+        return '[${signals.width - 1}:0] $signalName';
       } else {
         return signalName;
       }

test/assignment_test.dart

@@ -37,6 +37,7 @@ void main() {
     ];
     await SimCompare.checkFunctionalVector(exampleModule, vectors);
     final simResult = SimCompare.iverilogVector(
+      exampleModule,
       exampleModule.generateSynth(),
       exampleModule.runtimeType.toString(),
       vectors,

test/bus_test.dart

@@ -252,49 +252,6 @@ void main() {
   });
 
   group('simcompare', () {
-    final signalToWidthMap = {
-      'a': 8,
-      'b': 8,
-      'a_bar': 8,
-      'a_and_b': 8,
-      'a_b_joined': 16,
-      'a_plus_b': 8,
-
-      // Slicing
-      'a_shrunk1': 3,
-      'a_shrunk2': 2,
-      'a_shrunk3': 1,
-      'a_neg_shrunk1': 3,
-      'a_neg_shrunk2': 2,
-      'a_neg_shrunk3': 1,
-      // Reverse Slicing
-      'a_rsliced1': 5,
-      'a_rsliced2': 2,
-      'a_rsliced3': 1,
-      'a_r_neg_sliced1': 5,
-      'a_r_neg_sliced2': 2,
-      'a_r_neg_sliced3': 1,
-
-      // getRange
-      'a_range1': 3,
-      'a_range2': 2,
-      'a_range3': 1,
-      'a_neg_range1': 3,
-      'a_neg_range2': 2,
-      'a_neg_range3': 1,
-
-      // operator[]
-      'a_operator_indexing1': 1,
-      'a_operator_indexing2': 1,
-      'a_operator_indexing3': 1,
-      'a_operator_neg_indexing1': 1,
-      'a_operator_neg_indexing2': 1,
-      'a_operator_neg_indexing3': 1,
-
-      // Logic bus value Reversed
-      'a_reversed': 8,
-      'expression_bit_select': 4,
-    };
     test('NotGate bus', () async {
       final gtm = BusTestModule(Logic(width: 8), Logic(width: 8));
       await gtm.build();
@@ -306,8 +263,7 @@ void main() {
       ];
       await SimCompare.checkFunctionalVector(gtm, vectors);
       final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+          gtm, gtm.generateSynth(), gtm.runtimeType.toString(), vectors);
       expect(simResult, equals(true));
     });
 
@@ -324,8 +280,7 @@ void main() {
 
       await SimCompare.checkFunctionalVector(gtm, vectors);
       final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+          gtm, gtm.generateSynth(), gtm.runtimeType.toString(), vectors);
       expect(simResult, equals(true));
     });
 
@@ -343,8 +298,7 @@ void main() {
 
       await SimCompare.checkFunctionalVector(gtm, vectors);
       final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+          gtm, gtm.generateSynth(), gtm.runtimeType.toString(), vectors);
       expect(simResult, equals(true));
     });
 
@@ -382,8 +336,7 @@ void main() {
       ];
       await SimCompare.checkFunctionalVector(gtm, vectors);
       final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+          gtm, gtm.generateSynth(), gtm.runtimeType.toString(), vectors);
       expect(simResult, equals(true));
     });
 
@@ -421,8 +374,7 @@ void main() {
       ];
       await SimCompare.checkFunctionalVector(gtm, vectors);
       final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+          gtm, gtm.generateSynth(), gtm.runtimeType.toString(), vectors);
       expect(simResult, equals(true));
     });
 
@@ -436,8 +388,7 @@ void main() {
       ];
       await SimCompare.checkFunctionalVector(gtm, vectors);
       final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+          gtm, gtm.generateSynth(), gtm.runtimeType.toString(), vectors);
       expect(simResult, equals(true));
     });
 
@@ -475,8 +426,7 @@ void main() {
       ];
       await SimCompare.checkFunctionalVector(gtm, vectors);
       final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+          gtm, gtm.generateSynth(), gtm.runtimeType.toString(), vectors);
       expect(simResult, equals(true));
     });
 
@@ -492,8 +442,7 @@ void main() {
       ];
       await SimCompare.checkFunctionalVector(gtm, vectors);
       final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+          gtm, gtm.generateSynth(), gtm.runtimeType.toString(), vectors);
       expect(simResult, equals(true));
     });
 
@@ -507,8 +456,7 @@ void main() {
       ];
       await SimCompare.checkFunctionalVector(gtm, vectors);
       final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+          gtm, gtm.generateSynth(), gtm.runtimeType.toString(), vectors);
       expect(simResult, equals(true));
     });
 
@@ -524,8 +472,7 @@ void main() {
       ];
       await SimCompare.checkFunctionalVector(gtm, vectors);
       final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+          gtm, gtm.generateSynth(), gtm.runtimeType.toString(), vectors);
       expect(simResult, equals(true));
     });
 
@@ -537,8 +484,7 @@ void main() {
       ];
       await SimCompare.checkFunctionalVector(gtm, vectors);
       final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+          gtm, gtm.generateSynth(), gtm.runtimeType.toString(), vectors);
       expect(simResult, equals(true));
     });
   });

test/collapse_test.dart

@@ -48,7 +48,7 @@ void main() {
     ];
     await SimCompare.checkFunctionalVector(mod, vectors);
     final simResult = SimCompare.iverilogVector(
-        mod.generateSynth(), mod.runtimeType.toString(), vectors);
+        mod, mod.generateSynth(), mod.runtimeType.toString(), vectors);
     expect(simResult, equals(true));
   });
 

test/comb_math_test.dart

@@ -128,8 +128,7 @@ void main() {
     await SimCompare.checkFunctionalVector(mod, vectors);
 
     final simResult = SimCompare.iverilogVector(
-        mod.generateSynth(), mod.runtimeType.toString(), vectors,
-        signalToWidthMap: {'codepoint': 21, 'bytes': 32});
+        mod, mod.generateSynth(), mod.runtimeType.toString(), vectors);
     expect(simResult, equals(true));
   });
 
@@ -147,8 +146,7 @@ void main() {
 
     await SimCompare.checkFunctionalVector(mod, vectors);
     final simResult = SimCompare.iverilogVector(
-        mod.generateSynth(), mod.runtimeType.toString(), vectors,
-        signalToWidthMap: {'codepoint': 21, 'bytes': 32});
+        mod, mod.generateSynth(), mod.runtimeType.toString(), vectors);
     expect(simResult, equals(true));
   });
 
@@ -162,8 +160,7 @@ void main() {
     ];
     await SimCompare.checkFunctionalVector(mod, vectors);
     final simResult = SimCompare.iverilogVector(
-        mod.generateSynth(), mod.runtimeType.toString(), vectors,
-        signalToWidthMap: {'a': 8, 'b': 8});
+        mod, mod.generateSynth(), mod.runtimeType.toString(), vectors);
     expect(simResult, equals(true));
   });
 
@@ -177,8 +174,7 @@ void main() {
     ];
     await SimCompare.checkFunctionalVector(mod, vectors);
     final simResult = SimCompare.iverilogVector(
-        mod.generateSynth(), mod.runtimeType.toString(), vectors,
-        signalToWidthMap: {'a': 8, 'b': 8});
+        mod, mod.generateSynth(), mod.runtimeType.toString(), vectors);
     expect(simResult, equals(true));
   });
 
@@ -192,8 +188,7 @@ void main() {
     ];
     await SimCompare.checkFunctionalVector(mod, vectors);
     final simResult = SimCompare.iverilogVector(
-        mod.generateSynth(), mod.runtimeType.toString(), vectors,
-        signalToWidthMap: {'a': 8, 'b': 8});
+        mod, mod.generateSynth(), mod.runtimeType.toString(), vectors);
     expect(simResult, equals(true));
   });
 }

test/comb_mod_test.dart

@@ -69,8 +69,7 @@ void main() {
     ];
     await SimCompare.checkFunctionalVector(mod, vectors);
     final simResult = SimCompare.iverilogVector(
-        mod.generateSynth(), mod.runtimeType.toString(), vectors,
-        signalToWidthMap: {'a': 8, 'b': 8});
+        mod, mod.generateSynth(), mod.runtimeType.toString(), vectors);
     expect(simResult, equals(true));
   });
 
@@ -83,8 +82,7 @@ void main() {
     ];
     await SimCompare.checkFunctionalVector(mod, vectors);
     final simResult = SimCompare.iverilogVector(
-        mod.generateSynth(), mod.runtimeType.toString(), vectors,
-        signalToWidthMap: {'a': 8, 'b': 8});
+        mod, mod.generateSynth(), mod.runtimeType.toString(), vectors);
     expect(simResult, equals(true));
   });
 }

test/comparison_test.dart

@@ -51,11 +51,6 @@ void main() {
   tearDown(Simulator.reset);
 
   group('simcompare', () {
-    final signalToWidthMap = {
-      'a': 8,
-      'b': 8,
-    };
-
     test('compares', () async {
       final gtm = ComparisonTestModule(Logic(width: 8), Logic(width: 8));
       await gtm.build();
@@ -108,8 +103,7 @@ void main() {
       ];
       await SimCompare.checkFunctionalVector(gtm, vectors);
       final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+          gtm, gtm.generateSynth(), gtm.runtimeType.toString(), vectors);
       expect(simResult, equals(true));
     });
   });

test/conditionals_test.dart

@@ -185,8 +185,7 @@ void main() {
       ];
       await SimCompare.checkFunctionalVector(mod, vectors);
       final simResult = SimCompare.iverilogVector(
-          mod.generateSynth(), mod.runtimeType.toString(), vectors,
-          signalToWidthMap: {'d': 10, 'q': 10});
+          mod, mod.generateSynth(), mod.runtimeType.toString(), vectors);
       expect(simResult, equals(true));
     });
 
@@ -201,7 +200,7 @@ void main() {
       ];
       await SimCompare.checkFunctionalVector(mod, vectors);
       final simResult = SimCompare.iverilogVector(
-          mod.generateSynth(), mod.runtimeType.toString(), vectors);
+          mod, mod.generateSynth(), mod.runtimeType.toString(), vectors);
       expect(simResult, equals(true));
     });
 
@@ -216,7 +215,7 @@ void main() {
       ];
       await SimCompare.checkFunctionalVector(mod, vectors);
       final simResult = SimCompare.iverilogVector(
-          mod.generateSynth(), mod.runtimeType.toString(), vectors);
+          mod, mod.generateSynth(), mod.runtimeType.toString(), vectors);
       expect(simResult, equals(true));
     });
 
@@ -231,7 +230,7 @@ void main() {
       ];
       await SimCompare.checkFunctionalVector(mod, vectors);
       final simResult = SimCompare.iverilogVector(
-          mod.generateSynth(), mod.runtimeType.toString(), vectors);
+          mod, mod.generateSynth(), mod.runtimeType.toString(), vectors);
       expect(simResult, equals(true));
     });
 
@@ -248,8 +247,7 @@ void main() {
       ];
       await SimCompare.checkFunctionalVector(mod, vectors);
       final simResult = SimCompare.iverilogVector(
-          mod.generateSynth(), mod.runtimeType.toString(), vectors,
-          signalToWidthMap: {'d': 8, 'q': 8});
+          mod, mod.generateSynth(), mod.runtimeType.toString(), vectors);
       expect(simResult, equals(true));
     });
   });

test/counter_test.dart

@@ -72,9 +72,8 @@ void main() {
         Vector({'en': 0, 'reset': 0}, {'val': 5}),
       ];
       await SimCompare.checkFunctionalVector(counter, vectors);
-      final simResult = SimCompare.iverilogVector(
-          counter.generateSynth(), counter.runtimeType.toString(), vectors,
-          signalToWidthMap: {'val': 8});
+      final simResult = SimCompare.iverilogVector(counter,
+          counter.generateSynth(), counter.runtimeType.toString(), vectors);
       expect(simResult, equals(true));
     });
   });

test/counter_wintf_test.dart

@@ -81,8 +81,7 @@ void main() {
       ];
       await SimCompare.checkFunctionalVector(mod, vectors);
       final simResult = SimCompare.iverilogVector(
-          mod.generateSynth(), mod.runtimeType.toString(), vectors,
-          signalToWidthMap: {'val': 8});
+          mod, mod.generateSynth(), mod.runtimeType.toString(), vectors);
       expect(simResult, equals(true));
     });
   });

test/extend_test.dart

@@ -49,8 +49,7 @@ void main() {
         await mod.build();
         await SimCompare.checkFunctionalVector(mod, vectors);
         final simResult = SimCompare.iverilogVector(
-            mod.generateSynth(), mod.runtimeType.toString(), vectors,
-            signalToWidthMap: {'a': originalWidth, 'b': newWidth});
+            mod, mod.generateSynth(), mod.runtimeType.toString(), vectors);
         expect(simResult, equals(true));
       }
 
@@ -116,8 +115,7 @@ void main() {
         await mod.build();
         await SimCompare.checkFunctionalVector(mod, vectors);
         final simResult = SimCompare.iverilogVector(
-            mod.generateSynth(), mod.runtimeType.toString(), vectors,
-            signalToWidthMap: {'a': 8, 'b': updateWidth, 'c': 8});
+            mod, mod.generateSynth(), mod.runtimeType.toString(), vectors);
         expect(simResult, equals(true));
       }