FCVT.W.S instructions set invalid operation flag of fflags wrongly

[salaheddinhetalani]

Issue Description

FCVT.W.S instructions set invalid operation flag "NV" of fflags wrongly.

Component

Component:RTL

RISC-V Specification

The Zfinx extension adds all of the instructions that the F extension adds, except for the transfer instructions FLW, FSW, FMV.W.X, FMV.X.W, C.FLW[SP], and C.FSW[SP].

The Zfinx variants of these F-extension instructions have the same semantics, except that whenever such an instruction would have accessed an f register, it instead accesses the x register with the same number.

Steps to Reproduce

As shown below, the following sequence of instructions happens:

fcvt.w.s x1, x14, DYN -> fsqrt.s x0, x0, DYN

The instruction fcvt.w.s is decoded at t##0 and executed updating the integer register file at t##1 while setting the invalid flag NV of fflags CSR wrongly. Since the instruction has a dynamic rounding mode, the rounding mode of frm, round down RDN, is used.

Top Level Parameters

cv32e40p_wrapper #(
    .PULP_XPULP       (0),
    .PULP_CLUSTER     (0),
    .FPU              (1),
    .PULP_ZFINX       (1),
    .NUM_MHPMCOUNTERS (1)
)

Git Hash: d0d1c25
Flist: cv32e40p_fpu_manifest.flist
VCD: bug_10.vcd

---

Product: OneSpin 360 DV-Verify
App: Processor Verification App
Tool's version: 2022.3_1

[pascalgouedo]

Resolved with PR #860