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FMUL.S instructions set underflow flag of fflags wrongly #729
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Component:RTL
For issues in the RTL (e.g. for files in the rtl directory)
PARAM:FPU
Issue depends on the FPU parameter
Status:Resolved
Issue has been resolved, but closure is pending on git merge and/or issuer confirmation
Type:Bug
For bugs in the RTL, Documentation, Verification environment or Tool and Build system
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Component:RTL
For issues in the RTL (e.g. for files in the rtl directory)
PARAM:FPU
Issue depends on the FPU parameter
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Type:Bug
For bugs in the RTL, Documentation, Verification environment or Tool and Build system
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Signed-off-by: Pascal Gouedo <[email protected]>
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- Fix Underflow flag for MUL and DIV/SQRT operations (openhwgroup#94 openhwgroup#726 openhwgroup#729) - Fix for Float to Int conversion (openhwgroup#97 openhwgroup#83 openhwgroup#727) - Fixed unnecessary trailing semicolon (openhwgroup#99) Signed-off-by: Pascal Gouedo <[email protected]>
Resolved with PR #860 |
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Labels
Component:RTL
For issues in the RTL (e.g. for files in the rtl directory)
PARAM:FPU
Issue depends on the FPU parameter
Status:Resolved
Issue has been resolved, but closure is pending on git merge and/or issuer confirmation
Type:Bug
For bugs in the RTL, Documentation, Verification environment or Tool and Build system
Issue Description
FMUL.S instructions set underflow flag "UF" of fflags wrongly.
Component
Component:RTL
RISC-V Specification
Steps to Reproduce
As shown below, the following sequence of instructions happens:
The instruction
fmul.s
is decoded att##0
and executed updating the integer register file att##1
while setting the underflow flagUF
offflags
CSR wrongly.Top Level Parameters
Git Hash: d0d1c25
Flist: cv32e40p_fpu_manifest.flist
VCD: bug_12.vcd
Product: OneSpin 360 DV-Verify
App: Processor Verification App
Tool's version: 2022.3_1
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