NOT converts 0 to 0xFFFFFFFF, which is not what we want. Also this
commit removes setge and setuge optimisation which is never actually
selected.

Note that halfword load and store are not being selected at the moment.

UImm12 offset was not getting correctly set and Imm9
instructions were never getting selected. There was no
pattern for selecting Imm9 anyextending loads (fixed).

Complex float should be returned in registers, while complex double
should be returned by reference.

This has been copied from GCC:
https://github.com/MIPS/gcc/blob/mips/umips/gcc6_v12/gcc/config/mips/nanomips.h#L246

If return required more than 2 registers, nanoMIPS allocation would fail
on 3rd and would fall back to allocating MIPS registers.

It seems that O32 is default RetCC for more than O32 ABI. Make it not a
fallback exclusively for P32.

GP-relative load was not getting picked up because LWs9_NM was catching
everything with LWs9_NM $r1, 0($r2). In order to avoid this kind of
behaviour, catching loads/stores that have an immediate which is out of
range had to be split into a separate pattern match (for all loads and
stores).

This is done to fix CXX/basic/basic.lookup/basic.lookup.argdep/p2.cpp.
Fix was copied from AArch64 implementation, since it handles __va_list
very similarly to nanoMIPS.

This test seems to fail in the same manner for arm and thumb.

nanomips-elf-as cannot stream to stdout

The previous way messed with regular mips and made some tests fail.

nanoMIPS stack pointer supports 9-bit offset. This has to be properly
checked when setting scavenging frame index.

nanoMIPS GNU assembler doesn't support $0.

This is just for the sake of compiling code which uses this undocumented
GCC internal format.

Large aggregates need to be passed by reference. This also applies to
va_list, which was, instead of being passed by reference, defined as an
array type of length 1 and passed that way. This caused problems when
assigning one va_list variable to another.

In case we want to change allocation order by rearranging register, that
can be done using AltOrders. This commit also removes duplicate T8 and
T9 registers.

Stack adjustment sometimes isn't in the entry/return block, so it is
neccessary to check all blocks. This is usually in functions that have
early exits.

Previously generateSaveOrRestore assumed that it is processing either
entry or exit block and had assertions according to that. But since it's
now being executed on other basic blocks as well, it is neccessary to
change to assumption.

Compiler sometimes generated move instructions between return and stack
adjustment, which caused restore.jrc to be generated before those moves
and produced illegal code. This makes sure that restore.jrc is the very
last instruction generated.