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Flatten barstools into Chipyard #1855
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- Support byte-masked SRAM, yay - Also nuke a bunch of bugs
Move iocells to separate project root
Chisel3.6
Elaborating all macros in a single Circuit with an arbitrary (last) macro selected as the circuit main main cause some macros to be dropped, even with the DCEAnnotation. Work around this for now by elaborating each module in the macrocompiled circuit independently, then concatenating the verilog.
Fixes for IOCell + MacroCompiler
Dump per macro verilog (overridden by final verilog output)
Emit a empty HammerIR JSON when no macros to avoid downstream tool problems
- `IO` was moved from `chisel3.experimental` to `chisel3` - `DataMirror` was moved from `chisel3.experimental` to `chisel3.reflect`
Update deprecated APIs to prepare for Chisel 5
joonho3020
approved these changes
Apr 19, 2024
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SFTM on cursory review
abejgonzalez
approved these changes
Apr 19, 2024
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SFTM
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This makes it easier to move to chisel6 in the future.
The commit history from barstools is pulled in as well
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main
as the base branch?changelog:<topic>
label?changelog:
label?.conda-lock.yml
file if you updated the conda requirements file?Please Backport
?