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Flatten barstools into Chipyard #1855

Merged
merged 322 commits into from
Apr 20, 2024
Merged

Flatten barstools into Chipyard #1855

merged 322 commits into from
Apr 20, 2024
This pull request is big! We’re only showing the most recent 250 commits.

Commits on Oct 3, 2017

  1. Support non-prefixed ports

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  2. Finish rewriting in new format

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  3. Nuke hardcoded JSON tests from orbit

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  4. Add some documentation

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  5. Start cost function refactor

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  6. Bump mdf again

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  7. Add external metric

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  8. Implement cost selection from command line

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  9. Add sbt-assembly for making jar

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  10. Fix typo

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  11. Specify cost function from command line

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  12. Move notes to main file since they apply there as well

    @edwardcwang
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  13. Add cost function selection test

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  14. Implement command line cost metric selection

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  15. Trim redundant MDF field

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  16. Move cost metric to its own file

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  17. Test for non-empty Verilog

    @edwardcwang
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  18. Bump mdf

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  19. Add rocket-chip inspired tests

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  20. Re-implement parallel mapping 

    - Support byte-masked SRAM, yay
- Also nuke a bunch of bugs
    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  21. Add test from Donggyu

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  22. Enable some more tests

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  23. Bump mdf

    @edwardcwang
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  24. Add strict mode

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  25. Bump mdf again

    @edwardcwang
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  26. Not a scaladoc

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  27. Address review comments

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  28. Fix grammar

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  29. Bump mdf for the last time, for now

    @edwardcwang
    edwardcwang committed Oct 3, 2017
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  30. Update command line help

    @edwardcwang
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Commits on Oct 7, 2017

  1. Correct multi-ported memory compilation (#27) 

    * Correct multi-ported memory compilation

It was incorrectly splitting multiple times before. Fixed the issue and
added regression tests for this issue.

* Add 1 read 1 write test
    @edwardcwang
    edwardcwang authored Oct 7, 2017
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Commits on Dec 4, 2017

  1. Support firrtl output in command line for MacroCompiler (#28) 

    * Use the given port prefix (fix a bug preventing two unit tests from passing)
* Support firrtl output in addition to Verilog
    @edwardcwang
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Commits on Feb 17, 2018

  1. Add memory compiler to macros (#29) 

    * Add memory compiler to macros

* Removed weird spacing

* Make sramcompiler width/depth range inclusive

* Added sramcompiler test
    @azidar
    azidar authored Feb 17, 2018
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  2. Bump mdf to match master

    @edwardcwang
    edwardcwang committed Feb 17, 2018
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Commits on Mar 21, 2018

  1. Include macro compiler JAR compilation instructions

    @edwardcwang
    edwardcwang authored Mar 21, 2018
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Commits on Apr 26, 2018

  1. Fix corner case in compiling a small mem using a large lib (#32) 

    * Refactor bit pairs calculation into a separate function

* Minor clarifications

* Clarify MacroCompilerSpec helpers

* Add SmallTagArrayTest test

* Fix corner case in compiling a small mem using a large lib
    @edwardcwang
    edwardcwang authored Apr 26, 2018
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Commits on Oct 31, 2018

  1. Remove deprecated run-main

    @edwardcwang
    edwardcwang authored Oct 31, 2018
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Commits on Feb 6, 2019

  1. Overhaul CompilerMode parsing

    @edwardcwang
    edwardcwang committed Feb 6, 2019
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  2. Add options to force certain memories to lib or synflops

    @edwardcwang
    edwardcwang committed Feb 6, 2019
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Commits on Feb 13, 2019

  1. Refactor barstools for new versions of things. 

    - No handlebars (not being published for Scala 2.12)
- Update for new annotations APIs

Bump sbt-dependency-graph to 0.9.2 for this scala version
    @grebe @jwright6323
    grebe authored and jwright6323 committed Feb 13, 2019
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  2. Fix null pointer exception in options parser

    @grebe @jwright6323
    grebe authored and jwright6323 committed Feb 13, 2019
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  3. Run transforms in slightly different order 

    Also, don't rename TestHarness.
    @grebe @jwright6323
    grebe authored and jwright6323 committed Feb 13, 2019
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  4. Fix repl-seq-mem

    @grebe @jwright6323
    grebe authored and jwright6323 committed Feb 13, 2019
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  5. Refactor the harness generation; use upstream arguments and passes wh… 

    …ere appropriate
    @jwright6323
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  6. This compiles and works correctly, but is kind of hacky, and will bre… 

    …ak as soon as any additional external/blackbox modules are added to the test harness. The test harness should detect external modules and not rename them instead of what is happening here.
    @jwright6323
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  7. Add MemConf and change MacroCompiler to use a conf file instead of MD… 

    …F JSON
    @jwright6323
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  8. Don't run DCE && Profit

    @jwright6323
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  9. Use the correct 'magic values' for the port names 

    Ensure backwards compatiblity by using -m for MDF input and -n for conf
input. Also fix the naming scheme for memory ports.
    @jwright6323
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  10. Naming consistency (memMode -> memFormat)

    @jwright6323
    jwright6323 committed Feb 13, 2019
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  11. Style/Comments from review of #35

    @jwright6323
    jwright6323 committed Feb 13, 2019
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  12. Fixed index offset in mask port mapping. (#38) 

    Fixed index offset in mask port mapping.
    @jamesdunn @jwright6323
    jamesdunn authored and jwright6323 committed Feb 13, 2019
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Commits on Mar 2, 2019

  1. Add SimDTM to list of extmodules

    @colinschmidt
    colinschmidt committed Mar 2, 2019
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Commits on Mar 18, 2019

  1. Make SRAM per port clocks optional 

    Connects to whatever clock ports are available
    @colinschmidt
    colinschmidt committed Mar 18, 2019
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  2. Change cost to double from BigInt and fix default metric 

    I don't think it was adding anything and now we can get rid of
the weird +1/-1
    @colinschmidt
    colinschmidt committed Mar 18, 2019
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  3. Filter compiler libraries before mapping 

    The filter is always by family and maskability and then by any
integral mappings.
    @colinschmidt
    colinschmidt committed Mar 18, 2019
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  4. Fix forms of passes to happen before replseqmem 

    This ensures the conf file doesn't have any testharness
memories, which are too big and break downstream tools
    @colinschmidt
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  5. Fix cost metric for non Compiler libs 

    Also a small fix from reviewer
    @colinschmidt
    colinschmidt committed Mar 18, 2019
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  6. Fix unit tests update cost function once more 

    bump mdf to master
    @colinschmidt
    colinschmidt committed Mar 18, 2019
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  7. Avoid using the github redirect for mdf

    @colinschmidt @edwardcwang
    colinschmidt authored and edwardcwang committed Mar 18, 2019
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  8. Add Travis (#48)

    @colinschmidt
    colinschmidt authored Mar 18, 2019
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  9. stop exceptions on empty conf files (#43) 

    * stop exceptions on empty conf files

* emit empty verilog file | warn users

* put else's on same line as closing bracket
    @abejgonzalez @colinschmidt
    abejgonzalez authored and colinschmidt committed Mar 18, 2019
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  10. HighForm has whens so we need to check for instances there (#49) 

    Fixes a bug
    @colinschmidt
    colinschmidt authored Mar 18, 2019
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Commits on Mar 26, 2019

  1. Emit hammer IR from MacroCompiler (#50)

    @colinschmidt @edwardcwang
    colinschmidt authored and edwardcwang committed Mar 26, 2019
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Commits on Mar 28, 2019

  1. Fix annos (#53) 

    * Fixes #36 by using the renamemap
* Also fix harness passes annotation handling h/t azidar
* Remove old comment
    @colinschmidt
    colinschmidt authored Mar 28, 2019
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Commits on Mar 29, 2019

  1. Add options to emit top/harness firrtl and annotations (#54)

    @jwright6323
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Commits on May 14, 2019

  1. SRAM depth to bigint 

    max synflop depth support
Fix annotation mangling on the harness side
    @colinschmidt
    colinschmidt committed May 14, 2019
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  2. Upstream MemConf and use it (with some slight tweaks)

    @jwright6323 @colinschmidt
    jwright6323 authored and colinschmidt committed May 14, 2019
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Commits on Jul 30, 2019

  1. Filter all EmittedAnnotations from JSON emission (#64) 

    * Filter all EmittedAnnotations from JSON emission

* Filter more annotations
    @albert-magyar
    albert-magyar authored Jul 30, 2019
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Commits on Jul 31, 2019

  1. Coordinate Top and Harness generation (#63) 

    * Coordinate Top and Harness generation

* Update to use .f filename override annotations

* Move top generation to def to help GC
    @albert-magyar
    albert-magyar authored Jul 31, 2019
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Commits on Aug 17, 2019

  1. remove large annotations

    @abejgonzalez
    abejgonzalez committed Aug 17, 2019
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Commits on Aug 19, 2019

  1. Filter out all deleted annotations

    @albert-magyar
    albert-magyar committed Aug 19, 2019
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Commits on Oct 24, 2019

  1. Print the firrtl exception if we get one 

    Fixes #67
    @colinschmidt
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Commits on Oct 26, 2019

  1. Fix macrocompiler for RW mask port

    @abejgonzalez
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Commits on Oct 28, 2019

  1. Use x instead of e to match other case

    @colinschmidt
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  2. add test case

    @abejgonzalez
    abejgonzalez committed Oct 28, 2019
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  3. fix spacing

    @abejgonzalez
    abejgonzalez committed Oct 28, 2019
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Commits on Nov 4, 2019

  1. Merge pull request #69 from ucb-bar/abejgonzalez-patch-1 

    Fix macrocompiler for RW mask port
    @abejgonzalez
    abejgonzalez authored Nov 4, 2019
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Commits on Nov 5, 2019

  1. Fix MacroCompiler for CE-less Library Memories 

    If a memory doesn't have a mask and doesn't have a chip enable, make sure that you use the `mem` chip enable to connect to the `we` port on the `lib` memory. Fixes a bug where the `lib` `we` signal would be tied to the `mem` `wmode` signal but then the macro would have no `en` signal connected to it.
    @abejgonzalez
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  2. enforce re is disabled when we is enabled

    @abejgonzalez
    abejgonzalez authored Nov 5, 2019
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Commits on Nov 6, 2019

  1. Merge pull request #66 from ucb-bar/large-anno-remove 

    Remove large annotations
    @abejgonzalez
    abejgonzalez authored Nov 6, 2019
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  2. add test case for we bug

    @abejgonzalez
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Commits on Nov 7, 2019

  1. Merge pull request #70 from ucb-bar/abejgonzalez-patch-1 

    Fix MacroCompiler for CE-less Library Memories
    @abejgonzalez
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  2. Match inner variables

    @abejgonzalez
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  3. Merge pull request #68 from ucb-bar/print-firrtl-exception 

    Print the firrtl exception if we get one
    @abejgonzalez
    abejgonzalez authored Nov 7, 2019
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Commits on Dec 6, 2019

  1. Fix issues after chisel update for august 2019

    @colinschmidt
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  2. Updates for rocket-chip bump

    @colinschmidt
    colinschmidt committed Dec 6, 2019
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Commits on Dec 12, 2019

  1. Merge pull request #73 from ucb-bar/rc-bump-aug-2019 

    Rc bump aug 2019
    @colinschmidt
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Commits on Feb 12, 2020

  1. Correctly specify width of default zero output value (#74)

    @albert-magyar
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Commits on Feb 18, 2020

  1. Update to chisel 3.2.x

    @colinschmidt
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Commits on Feb 20, 2020

  1. Fix CI tests

    @colinschmidt
    colinschmidt committed Feb 20, 2020
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  2. Merge branch 'master' into bump_chisel_3.2.x

    @colinschmidt
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  3. Fix width of zeros after #74

    @colinschmidt
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Commits on Feb 26, 2020

  1. Merge pull request #75 from ucb-bar/bump_chisel_3.2.x 

    Update to chisel 3.2.x
    @colinschmidt
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Commits on Mar 17, 2020

  1. WIP; does not compile, but useful as a code review starting point

    @jwright6323
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Commits on Mar 19, 2020

  1. First pass that works

    @jwright6323
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  2. Allow naming, make the auto-clone IO method work

    @jwright6323
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Commits on Mar 30, 2020

  1. Rename example -> generic

    @jwright6323
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  2. Remove type casts; use a tuple match instead

    @jwright6323
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  3. Forgot to update the verilog modules

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Commits on Mar 31, 2020

  1. Code review feedback

    @jwright6323
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  2. More CR feedback, fix bug introduced in previous commit

    @jwright6323
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  3. Merge pull request #78 from ucb-bar/iocells 

    Add IO cell models
    @jwright6323
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Commits on Apr 18, 2020

  1. Update IOCell gen to handle abstract and async reset (#79)

    @davidbiancolin
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Commits on May 13, 2020

  1. Changes to tapeout transforms to support FIRRTL 1.3

    @albert-magyar
    albert-magyar committed May 13, 2020
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  2. Change macrocompiler to support FIRRTL 1.3 -- not backwards compatible

    @albert-magyar
    albert-magyar committed May 13, 2020
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  3. Provide MidForm circuit to MacroCompilerTransform

    @albert-magyar
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Commits on May 29, 2020

  1. Fix direction of output enable in output io cell

    @colinschmidt
    colinschmidt committed May 29, 2020
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Commits on May 30, 2020

  1. Merge pull request #82 from ucb-bar/fix-output-iocell 

    Fix direction of output enable in output io cell
    @abejgonzalez
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Commits on Jun 30, 2020

  1. Fix IOCells generation 

     * Fixes Bool wires matching both Reset and Bits
    @jerryz123
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Commits on Jul 3, 2020

  1. Merge pull request #85 from ucb-bar/iocells_fix 

    Fix IOCells generation
    @jerryz123
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Commits on Sep 4, 2020

  1. Clean up IOCell types and parameterization

    @jerryz123
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Commits on Sep 10, 2020

  1. This is mess clean it up

    @chick
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Commits on Sep 12, 2020

  1. Refactor tapeout for Chisel 3.4, Firrtl 1.4 

    - Remove clk package based on discussion with Colin
- Annotations need to be refactored to using latest API
  - Generally that involves making annos generated by a anonymous ChiselAnnotation
  - The chisel annotations will use RunFirrtlTransform to queue up its associated transform
  - Chisel annotation provieds toFirrtl to generate Firrtl form of annotation
- Usages of unapply on firrtl annotations cannot use generic unapply(target, transform, data) which has been eliminated
- Have transforms use with DependencyAPIMigration to avoid deprecated `form`s
- Added some 'see License comments
- TechnologyLocation section of AddIOPadsSpec does not currently run because there is no content for it.
  - Added some tests for annotation serialization here
    @chick
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Commits on Sep 14, 2020

  1. - FoundryPadsYaml would not parse yaml 

      - Made separate case class for data
  - Now parses
  - Fails later with UnknownType in firrt compiler
- Fixed similar parsing problem with PadPlacement
    @chick
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  2. Merge pull request #86 from ucb-bar/iocell-params 

    Clean up IOCell types and parameterization
    @jerryz123
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  3. Undo regression in iocell flexibility

    @jerryz123
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Commits on Sep 15, 2020

  1. Merge pull request #88 from ucb-bar/iocell-fix 

    Undo regression in iocell flexibility
    @jerryz123
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  2. Support plusarg_reader blackbox in the harness

    @jerryz123
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Commits on Sep 17, 2020

  1. Add explicit naming of IOs generated by generateIOFromSignal

    @jerryz123
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Commits on Sep 18, 2020

  1. Merge pull request #89 from ucb-bar/support-plusargs 

    Support plusarg_reader in TestHarness | explicitly name generated IOs
    @jerryz123
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Commits on Sep 28, 2020

  1. - Simplest way to make custom transforms run in same place as they di… 

    …d prior to Dependency API
    @chick
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  2. - Fixed ResetNSpec

    @chick
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Commits on Sep 29, 2020

  1. - Make transfrorms run in as close to same order as before 

    - Fix parsing of PadPlacement JSON
    @chick
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  2. - fix call to ceilLog2 in macros

    @chick
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Commits on Sep 30, 2020

  1. Remove all of the PadStuff

    @chick
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Commits on Oct 21, 2020

  1. Update MacroCompiler for Chisel 3.4

    @timsnyder-siv
    timsnyder-siv committed Oct 21, 2020
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Commits on Oct 23, 2020

  1. update build.sbt for Chisel3.4/FIRRTL1.4

    @timsnyder-siv
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  2. fixup! Update MacroCompiler for Chisel 3.4 

    Need to collect the annotations into a Seq.
Also updated the macros project tests.
    @timsnyder-siv
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  3. Merge branch 'firrtl-1.4-remove-clk-stuff' into chisel34

    @timsnyder-siv
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Commits on Nov 13, 2020

  1. Merge pull request #92 from sifive/chisel34 

    Update MacroCompiler for Chisel 3.4 / FIRRTL 1.4
    @chick
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Commits on Nov 20, 2020

  1. Merge remote-tracking branch 'origin/master' into firrtl-1.4-remove-c… 

    …lk-stuff
    @abejgonzalez
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Commits on Nov 26, 2020

  1. Bump to new dep. API | Automatically avoid renaming ExtMod's and circ… 

    …uit top mod
    @abejgonzalez
    abejgonzalez committed Nov 26, 2020
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Commits on Nov 28, 2020

  1. Add missing dependency to put AvoidExtModuleCollisions before ReplSeqMem

    @abejgonzalez
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Commits on Dec 1, 2020

  1. Use stable dep. versions | Small bumps/cleanup

    @abejgonzalez
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Commits on Dec 11, 2020

  1. Bump MDF for updated scala version

    @davidbiancolin
    davidbiancolin committed Dec 11, 2020
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  2. Fix ResetInv test

    @abejgonzalez
    abejgonzalez committed Dec 11, 2020
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  3. Generate LowFirrtl for Retime tests

    @abejgonzalez
    abejgonzalez committed Dec 11, 2020
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  4. Add invalidates=false to RetimeTransform

    @abejgonzalez
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Commits on Dec 13, 2020

  1. Merge pull request #87 from ucb-bar/firrtl-1.4-remove-clk-stuff 

    Move to Chisel 3.4, Firrtl 1.4, remove .clk and .pad stuff
    @abejgonzalez
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Commits on Dec 24, 2020

  1. bump mdf for ucb-bar/plsi-mdf#7

    @timsnyder-siv
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Commits on Feb 1, 2021

  1. Get rid of scalastyle checkers. 

    These are outdated and not used by the rest of the chisel family.
Add the scalafmt file that is used to fix code formatting. This will be used to regularize the code.
That work will be done by attrition.
    @chick
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Commits on Feb 2, 2021

  1. Merge pull request #94 from ucb-bar/get-rid-of-scala-style-checkers 

    Get rid of scalastyle checkers.
    @chick
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Commits on Feb 4, 2021

  1. Make the directory structure match the packages 

    All tests run as they did prior to the changes
    @chick
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  2. Reformat all scala files in iocells 

    - Mostly this reformat comments and large argument lists to classes and methods
    @chick
    chick committed Feb 4, 2021
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  3. Reformat all scala files in macros 

    - Mostly this reformat comments and large argument lists to classes and methods
    @chick
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  4. Reformat all scala files in tapeout 

    - Mostly this reformat comments and large argument lists to classes and methods
    @chick
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  5. Move to scalatest 3.2 

    Requires updating to AnyFlatSpec where used
And different import for Matchers
    @chick
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Commits on Feb 8, 2021

  1. Remove deprecated Driver stuff macros package 

    - Fix name reference and weird .get.get in CostMetric
- Update to DependencyAPIMigration
  - MacroCompilerTransform
  - MacroCompilerOptimizations
- Delete unused class MacroCompiler
- Remove use of ExecutionOptionsManager in object MacroCompiler
- Removed stack trace when no arguments from CLI, just give message requiring args
- Update version to 0.4-SNAPSHOT
    @chick
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Commits on Feb 9, 2021

  1. Modernize deprecated Chisel/Firrtl constructs 

    - Build out a stage for tapeout
  - Refactor annotation construction
  - Create a CLI handler
  - create a TapeOutStage
- Remove outputForm reference from EnumerateModules
- New GenerateTopAndHarness is fresh implmentation of Generate.scala
- GenerateTopSpec is a work in progress
    @chick
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  2. - changed directory path to iocells to use directories rather than do… 

    …tted name

- Changed packages in tapeout/transforms/utils/*.scala to be in their own package `utils`
    @chick
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Commits on Feb 10, 2021

  1. Merge pull request #97 from ucb-bar/fix-deprecations-1 

    Fix deprecations 1
    @chick
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  2. Merge branch 'master' into fix-deprecations-3

    @chick
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Commits on Feb 14, 2021

  1. - remove unused harnessTransforms 

    -
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  2. - Add rocketchip dependency to try and fix run problem in chipyard si… 

    …ms/vcs
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Commits on Feb 15, 2021

  1. - Don't carry over OutputFileAnnotaton to the harness phase of Genera… 

    …teTopAndHarness
    @chick
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  2. - Pull rocket dependency back out

    @chick
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Commits on Feb 16, 2021

  1. Add in missing transforms

    @chick
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Commits on Feb 17, 2021

  1. Get topAnnos into the mix

    @chick
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Commits on Feb 19, 2021

  1. Ignore GenerateTopAndHarness test for now

    @chick
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Commits on Feb 22, 2021

  1. Macrocompiler should prioritize memories with no masks with DefaultCo… 

    …stMetric
    @jerryz123
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  2. Merge remote-tracking branch 'origin/master' into mask_penalty

    @jerryz123
    jerryz123 committed Feb 22, 2021
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  3. Remove fully commented out original file Generate.scala

    @chick
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Commits on Feb 23, 2021

  1. Merge pull request #98 from ucb-bar/fix-deprecations-3 

    Fix deprecations 3
    @abejgonzalez
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Commits on Mar 12, 2021

  1. Merge pull request #99 from ucb-bar/mask_penalty 

    Macrocompiler should prioritize memories with no masks with DefaultCostMetric
    @jerryz123
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Commits on Jul 1, 2021

  1. Use github actions for testing 

    - Stripped down version from treadle
- commented out several sections
- delete travis test
- fix run-tests.yml
- Let's make this 3.
    @chick
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  2. Use github actions for testing 

    - Stripped down version from treadle
- commented out several sections
- delete travis test
- fix run-tests.yml
- Let's make this 3.
    @chick
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  3. Merge pull request #93 from sifive/bump_mdf 

    bump mdf for ucb-bar/plsi-mdf#7
    @chick
    chick authored Jul 1, 2021
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Commits on Jul 12, 2021

  1. Restore proper naming of harness annotation file

    @jwright6323
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  2. Merge pull request #104 from ucb-bar/harness_anno_fix 

    Restore proper naming of harness annotation file
    @jwright6323
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Commits on Jul 13, 2021

  1. Merge pull request #103 from ucb-bar/use-github-actions-for-ci 

    Use github actions for testing
    @chick
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  2. Fix bug that prunes InstanceTargets out of the AnnotationSeq in RePar… 

    …entCircuit
    @jwright6323
    jwright6323 committed Jul 13, 2021
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  3. Also make ReParentCircuit work on ReferenceTargets

    @jwright6323
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  4. Fix harness .fir file output location

    @jwright6323
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Commits on Jul 20, 2021

  1. Merge pull request #105 from ucb-bar/fix_reparent_circuit 

    Fix InstanceTarget annotations in ReParentCircuit
    @jwright6323
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  2. Merge pull request #106 from ucb-bar/fix_harness_fir 

    Fix harness .fir file output location
    @jwright6323
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Commits on Aug 6, 2021

  1. Moved a zillion files all over the place so that everything is now 

    in tapeout/src in the correct directory corresponding to internal packages.
Everything compiles and tests run
TODO:
- Figure out assembly step for MacroCompiler
- Does root project matter?
    @chick
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Commits on Aug 9, 2021

  1. iocell won't run without this syntax 

    IntelliJ flags this as error, even though it compiles and runs
    @chick
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  2. Add some missing resources

    @chick
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Commits on Aug 10, 2021

  1. Add setting to have sbt not exit 

    if a program calls System.exit
Without this a useless and misleading log4j error is reported.
    @chick
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  2. IOCell toBool => asBool 

    MacroCompiler needs more specific firrtl.Utils imports, Comment out legalize
SynFlops more precise imports
YamlHelpers use FileUtils
ResetInverter LegacyModule => Module
Retime use Module instead of LegacyModule
YamlHelpers uses FileUtils instead of getResource
ResetInvert use Module instead of LegacyModule
Masks add scalatest wrappers for getting better test reports
SpecificExamples drop tapeout prefix, and add scalatest blocks
GenerateSpec, let ChiselStage emit the firrt directly to target dir, add some actual tests that files were created
GenerateTopSpec use FileUtils
FlipChipMacroSpec use FileUtils
IOPropertiesSpec use FileUtils
    @chick
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  3. Move src/ from tapeout to top level 

    get rid of root
    @chick
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  4. MultiPort remove random println 

    GenerateSpec fix so "generate top test" does not rely on side-effects of previous test
GenerateTopSpec fix so it creates needed input file itself, does not rely on other tests to do that
    @chick
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Commits on Aug 11, 2021

  1. GenerateTopSpec get rid of Console.withOut

    @chick
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Commits on Aug 12, 2021

  1. Merge pull request #109 from ucb-bar/move-src-to-toplevel 

    Unify barstools into single src tree that matches package structure
    @chick
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Commits on Aug 16, 2021

  1. Adding support for Scala 2.13 

    Mostly import changes
Some formatting changes
Runs +test
    @chick
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  2. Merge pull request #111 from ucb-bar/scala-2.13 

    Adding support for Scala 2.13
    @ekiwi
    ekiwi authored Aug 16, 2021
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  3. Formatting code to chisel standard 

    - ran sbt scalafmtAll
  - lot of small formatting changes
- added test that code must stay formatted
  - part of github actions workflow
    @chick
    chick committed Aug 16, 2021
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Commits on Aug 17, 2021

  1. Fix all warnings in barstool.macros._ 

    - Fixed up all warnings in barstools macros package
- mostly public method return types
- removed lot's of extraneous parens and braces
- Made code cleaner using more explicit macros
- Fixed warnings in 2.13 that will likely turn into errors in future
    @chick
    chick committed Aug 17, 2021
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  2. This file seems to have missed a scalafmt pass

    @chick
    chick committed Aug 17, 2021
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  3. Fix scalafmt check

    @chick
    chick committed Aug 17, 2021
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  4. Oops, missed needs in all steps passed

    @chick
    chick committed Aug 17, 2021
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Commits on Aug 18, 2021

  1. Merge pull request #112 from ucb-bar/macro-code-cleanup 

    Fix all warnings in barstool.macros._
    @chick
    chick authored Aug 18, 2021
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Commits on Feb 2, 2022

  1. Remove sbt subproject "tapeout" 

    Now barstools should be easier to compose in multi-project sbt projects,
such as Chipyard.

Resolves ucb-bar/barstools#117.
    Tynan McAuley committed Feb 2, 2022
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  2. Make readme consistent with new sbt setup

    Tynan McAuley committed Feb 2, 2022
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Commits on Feb 3, 2022

  1. Add Chisel compiler plugin 

    See here for more info: https://github.com/chipsalliance/chisel3#build-your-own-chisel-projects
    Tynan McAuley committed Feb 3, 2022
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Commits on Feb 8, 2022

  1. Bump Chisel versions to x.5.1

    Tynan McAuley committed Feb 8, 2022
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Commits on Feb 11, 2022

  1. Merge pull request #118 from tymcauley/remove-sbt-subproject 

    Remove sbt subproject "tapeout"
    @abejgonzalez
    abejgonzalez authored Feb 11, 2022
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Commits on Oct 8, 2022

  1. No-op barstools SFC compiler

    @abejgonzalez
    abejgonzalez committed Oct 8, 2022
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Commits on Oct 10, 2022

  1. Attempt at checking for Fixed types

    @abejgonzalez
    abejgonzalez committed Oct 10, 2022
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Commits on Dec 23, 2022

  1. Add back HarnessConf

    @joonho3020
    joonho3020 committed Dec 23, 2022
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Commits on Dec 24, 2022

  1. Remove CheckForUnsupportedFirtoolTypes

    @joonho3020
    joonho3020 committed Dec 24, 2022
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  2. Fix formatting

    @joonho3020
    joonho3020 committed Dec 24, 2022
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  3. Remove GenerateTopSpec.scala test as the FIRRTL passes are removed

    @joonho3020
    joonho3020 committed Dec 24, 2022
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Commits on Dec 28, 2022

  1. Remove executeTop & make everything to execute

    @joonho3020
    joonho3020 committed Dec 28, 2022
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  2. Revert "Remove executeTop & make everything to execute" 

    This reverts commit 5af7f21.
    @joonho3020
    joonho3020 committed Dec 28, 2022
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  3. Fix dump to dumpAnnos

    @joonho3020
    joonho3020 committed Dec 28, 2022
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Commits on Dec 29, 2022

  1. Remove all passes again | rename GenerateTopAndHarness to GenerateMod… 

    …elStageMain
    @joonho3020
    joonho3020 committed Dec 29, 2022
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  2. Fixes test for CI

    @joonho3020
    joonho3020 committed Dec 29, 2022
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Commits on Jan 9, 2023

  1. Merge pull request #123 from ucb-bar/remove-barstools-compiler 

    CIRCT Integration
    @jerryz123
    jerryz123 authored Jan 9, 2023
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Commits on Feb 6, 2023

  1. Run RemoveValidIf pass for updated CIRCT

    @abejgonzalez
    abejgonzalez committed Feb 6, 2023
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  2. Merge remote-tracking branch 'origin/master' into run-extra-passes

    @abejgonzalez
    abejgonzalez committed Feb 6, 2023
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Commits on Feb 10, 2023

  1. Merge pull request #125 from ucb-bar/run-extra-passes

    @harrisonliew
    harrisonliew authored Feb 10, 2023
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Commits on Feb 21, 2023

  1. remove duplicate compiler annotation

    @joonho3020
    joonho3020 committed Feb 21, 2023
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Commits on Feb 23, 2023

  1. Update scala/sbt/chisel versions 

    The previous setup used Scala 2.12 even though Chipyard was trying to
override it to use 2.13.10.

Also sync Chisel minor versions with Chipyard, and update to a recent
sbt version.
    @tymcauley
    tymcauley committed Feb 23, 2023
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  2. Run scalafmt after scala version update

    @tymcauley
    tymcauley committed Feb 23, 2023
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  3. Remove unused test file 

    This file is breaking the test build, the class it is testing was
removed in df3232f.
    @tymcauley
    tymcauley committed Feb 23, 2023
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Commits on Mar 1, 2023

  1. Merge pull request #127 from tymcauley/use-scala-2.13 

    Update scala/sbt/chisel versions, fix CI
    @abejgonzalez
    abejgonzalez authored Mar 1, 2023
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  2. merge master

    @joonho3020
    joonho3020 committed Mar 1, 2023
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Commits on Mar 2, 2023

  1. Merge pull request #126 from ucb-bar/rm-duplicate-compiler-anno 

    Remove duplicate compiler annotation
    @abejgonzalez
    abejgonzalez authored Mar 2, 2023
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Commits on Mar 3, 2023

  1. Update build.sbt for sbt-assembly

    @abejgonzalez
    abejgonzalez committed Mar 3, 2023
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Commits on Mar 18, 2023

  1. Add name to IOCell definition

    Kevin Anderson committed Mar 18, 2023
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  2. formatting fix

    Kevin Anderson committed Mar 18, 2023
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  3. Code improvement; define IOCell name as Option and place in trait to … 

    …reduce code modifications
    Kevin Anderson committed Mar 18, 2023
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  4. format IOCell.scala

    Kevin Anderson committed Mar 18, 2023
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  5. Merge pull request #129 from kevindna/master 

    Add name to IOCell definition
    @kevindna
    kevindna authored Mar 18, 2023
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Commits on May 18, 2023

  1. Merge pull request #130 from ucb-bar/sbt-assembly 

    Update build.sbt for sbt-assembly
    @abejgonzalez
    abejgonzalez authored May 18, 2023
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Commits on May 31, 2023

  1. move iocells to separate "project" root

    @ethanwu10
    ethanwu10 committed May 31, 2023
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Commits on Jun 21, 2023

  1. asBool() to asBool

    @jerryz123
    jerryz123 committed Jun 21, 2023
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Commits on Jul 9, 2023

  1. Merge pull request #131 from ucb-bar/move-iocells 

    Move iocells to separate project root
    @jerryz123
    jerryz123 authored Jul 9, 2023
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Commits on Jul 10, 2023

  1. Merge remote-tracking branch 'origin/master' into chisel3.6

    @jerryz123
    jerryz123 committed Jul 10, 2023
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Commits on Jul 12, 2023

  1. Remove firrtl_interpreter tests

    @jerryz123
    jerryz123 committed Jul 12, 2023
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Commits on Jul 26, 2023

  1. Merge pull request #132 from ucb-bar/chisel3.6 

    Chisel3.6
    @jerryz123
    jerryz123 authored Jul 26, 2023
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Commits on Jul 30, 2023

  1. Generate 1 file per generic IOCell

    @jerryz123
    jerryz123 committed Jul 30, 2023
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  2. Macrocompiler: FIRRTL-elab macros 1-at-a-time 

    Elaborating all macros in a single Circuit with an arbitrary (last) macro
selected as the circuit main main cause some macros to be dropped, even with
the DCEAnnotation. Work around this for now by elaborating each module in the
macrocompiled circuit independently, then concatenating the verilog.
    @jerryz123
    jerryz123 committed Jul 30, 2023
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Commits on Jul 31, 2023

  1. Delete IOCell.v

    @jerryz123
    jerryz123 committed Jul 31, 2023
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  2. Merge pull request #133 from ucb-bar/fixes 

    Fixes for IOCell + MacroCompiler
    @jerryz123
    jerryz123 authored Jul 31, 2023
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Commits on Oct 16, 2023

  1. Dump per macro verilog (overridden by final verilog output)

    @abejgonzalez
    abejgonzalez committed Oct 16, 2023
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  2. Merge pull request #134 from ucb-bar/intermediate-dump-vlog 

    Dump per macro verilog (overridden by final verilog output)
    @abejgonzalez
    abejgonzalez authored Oct 16, 2023
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Commits on Oct 19, 2023

  1. Emit a empty HammerIR JSON when no macros to avoid downstream tool pr… 

    …oblems
    @jerryz123
    jerryz123 committed Oct 19, 2023
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  2. Merge pull request #135 from ucb-bar/empty-hammerir 

    Emit a empty HammerIR JSON when no macros to avoid downstream tool problems
    @harrisonliew
    harrisonliew authored Oct 19, 2023
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Commits on Jan 3, 2024

  1. Update deprecated APIs to prepare for Chisel 5 

    - `IO` was moved from `chisel3.experimental` to `chisel3`
- `DataMirror` was moved from `chisel3.experimental` to `chisel3.reflect`
    @tymcauley
    tymcauley committed Jan 3, 2024
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  2. Merge pull request #136 from tymcauley/chisel-5-prep 

    Update deprecated APIs to prepare for Chisel 5
    @jerryz123
    jerryz123 authored Jan 3, 2024
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Commits on Apr 19, 2024

  1. Merge remote-tracking branch 'barstools/master' into flatten-barstools

    @jerryz123
    jerryz123 committed Apr 19, 2024
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  2. Move IOCell files

    @jerryz123
    jerryz123 committed Apr 19, 2024
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  3. Delete useless files from barstools merge

    @jerryz123
    jerryz123 committed Apr 19, 2024
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  4. Move barstools tapeout src to tools/tapeout

    @jerryz123
    jerryz123 committed Apr 19, 2024
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  5. Remove barstools tests

    @jerryz123
    jerryz123 committed Apr 19, 2024
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  6. Delete barstools submodule

    @jerryz123
    jerryz123 committed Apr 19, 2024
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  7. Fixes for in-tree barstools

    @jerryz123
    jerryz123 committed Apr 19, 2024
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  8. Update docs to reflect in-tree barstools

    @jerryz123
    jerryz123 committed Apr 19, 2024
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