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submodule(difftest): bump difftest
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* difftest commit: ca4fce1867b23ebd9af27a4fa8627d2787bbee3a

including:
* fix(config): allow 8GB memory as default for unknown CPUs (#466)
* fix(csr): add support non register interrupt pending (#465)
* fix(csr): fix struct non-reg interrupt pending to order (#469)
* palladium: Build DPILIB_EMU shared library as separated targets (#468)
* Difftest: Use file API compatible with with Java8 (#467)
* Batch: pack Batch param to facilitate migration between DPIC/PCIe
  (#474)
* fix(cmo): add cmo inval event
* feat(mem): add optional ref func ref_memcpy_init (#475)
* Merge pull request #476 from OpenXiangShan/fix-cmo
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@sinceforYy
sinceforYy committed Sep 27, 2024
1 parent 01b0b75 commit a3315f6
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion difftest
Submodule difftest updated 16 files
+3 −3 .github/workflows/main.yml
+1 −0 README.md
+4 −4 config/config.h
+5 −3 palladium.mk
+6 −5 src/main/scala/Batch.scala
+15 −0 src/main/scala/Bundles.scala
+34 −31 src/main/scala/DPIC.scala
+12 −0 src/main/scala/Difftest.scala
+11 −14 src/main/scala/Gateway.scala
+5 −2 src/test/csrc/common/perf.cpp
+2 −0 src/test/csrc/common/perf.h
+71 −21 src/test/csrc/difftest/difftest.cpp
+10 −1 src/test/csrc/difftest/difftest.h
+37 −10 src/test/csrc/difftest/refproxy.h
+2 −2 src/test/csrc/verilator/emu.cpp
+3 −1 src/test/scala/DifftestTop.scala

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