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Releases: openhwgroup/cvfpu

v0.8.1

30 Aug 09:09
79e4531
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Create release 0.8.1:

  • Fix Underflow flag for MUL and DIV/SQRT operations (#94 #726 #729)
  • Fix for Float to Int conversion (#97 #83 #727)
  • Fixed unnecessary trailing semicolon (#99)

v0.8.0

19 Jun 08:38
d829f38
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Create release 0.8.0:

  • Add external reg enable to slices (#89)
  • Integrate new 32b divider (#79)
  • Moved @lucabertaccini to Authors
  • Added Pasquale Davide Schiavone and Pascal Gouedo as maintainers
  • multifmt slice uses wrong FP width for third operand (#86)
  • Fix DivSqrt lanes synchronization (#90)

v0.7.0

20 Mar 10:54
3116391
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Create release 0.7.0:

  • Align CVFPU to RVV requirements (ARA branch merged)
  • Fix f2i cast edge cases
  • Fix RDN bug in floating-point multiplications
  • Fix shift amount width in fma and fma_multi

v0.6.6

19 Apr 15:34
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Changed

  • ⬆️ [common_cells] Bump common cells version (#44)

v0.6.4

05 Oct 07:53
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Fixed

  • 🔧 Updated dependencies for Bender and IPApproX (#37)
  • ⬆️ [fpu_div_sqrt_mvp] Bump for formal version number

v0.6.3

02 Oct 18:51
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Fixed

  • 👕 Fix undriven signals for inactive case in fpnew_fma_multi
  • 👕 Fix potentially uncovered case item in fpnew_pkg
  • 👕 Undriven unused portions of signals in multi-format slices
  • 👕 Undriven portions of the result for non-divisible unit width & format width in multi-format slices
  • ⬆️ [fpu_div_sqrt_mvp] Bumped to fix signalling for underflows

v0.6.2

02 Jun 13:12
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Changed

  • 🐛 Number of pipeline registers in multi-format units is the maximum of all contained formats instead of the first format marked MERGED

Fixed

  • 📚 Typo in changelog
  • 🐛 Missing type cast breaking simulation in VCS (#24)

v0.6.1

10 Jul 15:45
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Fixed

  • 🐛 A bug where the div/sqrt unit could lose operations in flight

v0.6.0

04 Jul 12:42
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New in 0.6.0

Changed

  • ♻️ Pipelines are generated in the datapath modules instead of separate instances

Fixed

  • 👾 Don't care assignments to structs have been expanded for better tool support (#14)
  • 🐛 Undriven busy signal in output pipeline bypass
  • 📚 Typo in the documentation about the multiply operation
  • 🐛 Generation of merged slices when the first package format is disabled
  • 👾 Potential simulation/synthesis mismatch of the UF flag
  • 👕 Various linter warnings
  • 📚 Documentation to reflect on updated pipeline distribution order
  • ⬆️ [fpu_div_sqrt_mvp] Bumped to fix linter warnings
  • 🔧 [Bender] Fixed dependencies for Bender (#15)

Removed

  • 🔥 Currently unused modules: fpnew_pipe*, fpnew_{f2i,f2f,i2f}_cast

Other changes since 0.5.0

Added

  • 📚 Documentation about multi-format operations
  • 📚 Extended pipelining description slightly
  • 📚 Extended semantic versioning declaration in changelog

Changed

  • ✨ Don't care logic value can be changed from the package now
  • 🐎 Default pipeline config in the package is now BEFORE
  • 📚 Updated diagrams in architecture documentation

Fixed

  • 👾 Don't care values are assigned '1 instead of 'X by default
  • 🐛 UF flag handling according to IEEE754-2008 (#11)
  • 🔧 ips_list.yml entry for updated common_cells
  • 🐛 Internal pipeline bypass in cast unit
  • 🔧 Include path for common_cells in src_files.yml
  • ⬆️ [common_cells] Bumped to fix src_files.yml bugs
  • ⬆️ [fpu_div_sqrt_mvp] Bumped to fix linter warnings

v0.5.6

12 Jun 15:34
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Changed

  • ✨ Don't care logic value can be changed from the package now
  • 🐎 Default pipeline config in the package is now BEFORE

Fixed

  • 👾 Don't care values are assigned '1 instead of 'X by default