v0.6.4

👀 What's Changed

This release mainly fixes some bugs, most notably the loss of clocking information after apply_gate_library. However, also some small features were added like two new distance functions and crossing counting in gate_level_layout.

Full CHANGELOG: v0.6.3...v0.6.4
Many thanks to all contributors!

✨ Features and Enhancements

• ✨ Track number of crossings @simon1hofmann (#514)
• ✨ Squared Euclidean and Chebyshev distance functions @marcelwa (#512)

🐛 Bug Fixes

• 🐛 Fixed disappearing clocking schemes when applying a gate library @marcelwa (#515)
• 📝 Fix a few oversights in the RTD documentation of SiDB simulation functionality @marcelwa (#513)
• ✏️ Fixed a typo in robustness domain analysis @marcelwa (#511)
• 🚨 clang-tidy warnings @simon1hofmann (#507)

📝 Documentation

• 📝 Fix a few oversights in the RTD documentation of SiDB simulation functionality @marcelwa (#513)
• 📝 Add gold to README and docs @simon1hofmann (#508)

⬆️ Dependencies

• ⬆️ Bump libs/pybind11 from a1d0091 to c2291e5 in the submodules group @dependabot (#509)

v0.6.3

👀 What's Changed

Compared to the previous point releases, this one introduces several larger and more impactful features.

1. Graph-Oriented Layout Design (GOLD)
   This release includes the introduction of GOLD, an innovative algorithm designed for gate-level layout creation. GOLD strikes a balance between runtime efficiency and result quality, making it ideal for medium-sized inputs that are too complex for exact methods.

2. Defect-Aware On-the-Fly SiDB Circuit Design
   We’ve added support for defect-aware circuit design that enables precise, dot-level composition even in the presence of atomic defects. This approach doesn't rely on a pre-defined gate library; instead, it dynamically generates one, guided by physical simulations.

3. Multi-Dimensional Operational Domain Computation
   The operational domain computation feature now supports multidimensional sweeps, providing more flexibility and unprecedented insight into SiDB reliability. Additionally, users not utilizing execution policies will notice a significant performance boost.

As always, this release also includes numerous bug fixes, updates, and other changes, detailed below.

Full CHANGELOG: v0.6.2...v0.6.3
Many thanks to all contributors!

✨ Features and Enhancements

• ✨ Extended Time-to-Solution Function @Drewniok (#500)
• ✨ Multi-dimensional operational domain computation @marcelwa (#493)
• ✨ Defect-aware on-the-fly SiDB circuit designer @Drewniok (#317)
• ✨ Planar Graph-Oriented Layout Design @simon1hofmann (#497)
• ✨ Planar Post-Layout Optimization @simon1hofmann (#496)
• ✨ Graph-Oriented Layout Design (GOLD) @simon1hofmann (#456)
• ✨ Displacement Robustness Domain Simulation @Drewniok (#416)
• ✨ Algorithm for finding valid physical parameters for a given charge distribution. @Drewniok (#424)
• ✨ Flag for optimizing POs only @simon1hofmann (#461)

⚡️ Performance

• ✨ Multi-dimensional operational domain computation @marcelwa (#493)
• 👷 Disabled running computationally intensive unit tests via the CI in Debug build mode @Drewniok (#486)
• ⚡ Cleanup dangling PIs @simon1hofmann (#452)

🐛 Bug Fixes

• 🐛 clang-tidy comments were not posted @simon1hofmann (#505)
• 🐛 Fixed an RST documentation bug that prevented exact and exact_with_blacklist from being rendered properly @marcelwa (#506)
• 🎨 Utilizing tolerance to mitigate floating-point inaccuracies @Drewniok (#483)
• 🚸 Add warning for leak sanitizer usage with AppleClang @Drewniok (#482)
• 🚨 Fixed compiler warnings @simon1hofmann (#480)
• 📝 Update docstring generator to include target branch for push @Drewniok (#477)
• 🐛 Fixed multiple post_layout_optimization bugs @simon1hofmann (#472)
• 🐛 Multi-output nodes @simon1hofmann (#451)
• ⚡ Enable relocation of all 2-input gates during post_layout_optimization @simon1hofmann (#453)

📝 Documentation

• 🐛 Fixed a RST documentation bug that prevented exact and exact_with_blacklist to be rendered properly @marcelwa (#506)
• 📝 Update hexagonalization image @simon1hofmann (#444)

👷 CI

• 👷 Updated the Ubuntu CI to include 24.04 and newer compiler versions @marcelwa (#466)
• 👷 Update GCC versions on macOS CIs @marcelwa (#499)
• ⬆️ Upgrade Z3 to Version 4.13.0 in CLI Workflow and Docker. @Drewniok (#498)
• ⬆️ Bump pypa/cibuildwheel from 2.19.2 to 2.20.0 in the github-actions group @dependabot (#494)
• 💚 Update python version for sphinx-doc @Drewniok (#492)
• 💚 Added Python Setup to CI Workflow @Drewniok (#490)
• 👷 Disabled running computationally intensive unit tests via the CI in Debug build mode @Drewniok (#486)
• 📝 Run python docstring generator on forks during PRs @simon1hofmann (#475)
• ⬆️ Bump pypa/cibuildwheel from 2.19.1 to 2.19.2 in the github-actions group @dependabot (#471)
• 💚 Update CodeQL workflow to avoid memory issue @Drewniok (#468)
• ⬆️ Bump pypa/cibuildwheel from 2.18.1 to 2.19.1 in the github-actions group @dependabot (#457)
• ⬆️ Bump pre-commit hooks @pre-commit-ci (#455)
• ⬆️ Bump pypa/cibuildwheel from 2.18.0 to 2.18.1 in the github-actions group @dependabot (#445)

⬆️ Dependencies

17 changes

• ⬆️ Bump sphinx from 7.4.7 to 8.0.2 in /docs in the documentation group @dependabot (#488)
• ⬆️ Bump the submodules group with 2 updates @dependabot (#502)
• ⬆️ Bump pypa/cibuildwheel from 2.19.2 to 2.20.0 in the github-actions group @dependabot (#494)
• ⬆️ Bump the submodules group with 2 updates @dependabot (#495)
• ⬆️ Bump the submodules group across 1 directory with 2 updates @dependabot (#491)
• ⬆️ Bump the submodules group with 2 updates @dependabot (#484)
• ⬆️ Bump sphinx from 7.4.6 to 7.4.7 in /docs in the documentation group @dependabot (#485)
• ⬆️ Bump libs/pybind11 from 50acb81 to 6d4805c in the submodules group @dependabot (#478)
• ⬆️ Bump sphinx from 7.3.7 to 7.4.6 in /docs in the documentation group @dependabot (#479)
• ⬆️ Bump the submodules group with 3 updates @dependabot (#473)
• ⬆️ Bump pypa/cibuildwheel from 2.19.1 to 2.19.2 in the github-actions group @dependabot (#471)
• ⬆️ Bump the submodules group with 2 updates @dependabot (#470)
• ⬆️ Bump pypa/cibuildwheel from 2.18.1 to 2.19.1 in the github-actions group @dependabot (#457)
• ⬆️ Bump the submodules group across 1 directory with 2 updates @dependabot (#467)
• ⬆️ Bump the submodules group across 1 directory with 5 updates @dependabot (#459)
• ⬆️ Bump the submodules group with 2 updates @dependabot (#446)
• ⬆️ Bump pypa/cibuildwheel from 2.18.0 to 2.18.1 in the github-actions group @dependabot (#445)

v0.6.2

👀 What's Changed

This release fixes some smaller inconsistencies and enables a more intuitive usage of certain types in pyfiction.

✨ Features and Enhancements

• 🐍 Minor fixes and change of template parameter of BDL pairs. @Drewniok (#442)
• ⚗️ Added a runtime experiment script. @Drewniok (#441)

Full CHANGELOG: v0.6.1...v0.6.2
Many thanks to all contributors!

v0.6.1

👀 What's Changed

This is a minor bugfix release, mainly to fix the deployment of wheels to PyPI. Due to the new way GitHub actions handle artifacts, our wheels were constantly overwritten by ones compiled later. This is now fixed. Many thanks to @simon1hofmann for reporting and fixing this issue!

Full CHANGELOG: v0.6.0...v0.6.1
Many thanks to all contributors!

✨ Features and Enhancements

• ✨ Added truth table helpers for 3-input functions @marcelwa (#430)

🐛 Bug Fixes

• 🐛 Images on PyPI @simon1hofmann (#440)
• 🐛 PyPI Deployment for multiple operating systems @simon1hofmann (#431)

📝 Documentation

• 🐛 Images on PyPI @simon1hofmann (#440)
• 📝 Added more physical design cli commands to docs @simon1hofmann (#435)
• 📝 Added more physical design algorithms to the README @simon1hofmann (#434)

👷 CI

• ⬆️ Bump the github-actions group with 2 updates @dependabot (#439)
• 🎨 Added emojis to CI/CD @simon1hofmann (#433)
• 👷 Limit triggering of the pyfiction deployment CI @simon1hofmann (#436)

⬆️ Dependencies

• ⬆️ Bump libs/pybind11 from 7502577 to aa98d95 in the submodules group @dependabot (#438)
• ⬆️ Bump the github-actions group with 2 updates @dependabot (#439)
• ⬆️ Bump the submodules group with 3 updates @dependabot (#429)

v0.6.0

When it comes to the past, everyone writes fiction. ― Stephen King

👀 What's Changed

We keep saying that but this latest release of fiction is again the biggest one yet 💪 It is packed with another year's worth of research and marks a milestone on our mission to bring you the best FCN framework in the world 🌍 Let's dive into v0.6.0 together.

Python Bindings

A long time in the making, finally official: Python bindings for fiction's C++ header-only library 🐍 You can now combine the flexibility of Python's ecosystem with the performance of C++ to explore the world of FCN for yourself. Since we publish pre-built wheels on PyPI, utilizing fiction in your project is merely a pip call away:

pip install mnt.pyfiction

Many, many thanks to @Drewniok and @simon1hofmann who contributed greatly to the bindings! 🙏

SiDB Simulation

We doubled down on what we started: @Drewniok made sure that SiDB simulation in fiction has never been more powerful. This release includes his exhaustive ground-state simulation engine QuickExact, the fastest in the world! ⚡ It is also available as a plugin for SiQAD thanks to @samuelngsh's guidance.

Furthermore, for the first time ever, we feature temperature-aware and atomic defect-aware simulation, automatic exhaustive gate design, and efficient operational domain computation algorithms. Moreover, all these methods now work on the H-Si(100)-2x1 and H-Si(111)-1x1 lattice orientations. Many thanks to @samuelngsh for the ongoing collaboration!

Physical Design

Naturally, we kept pursuing our goal of closing the design gap between conventional VLSI and FCN. @simon1hofmann brings you his post-layout optimization and wiring reduction algorithms that greatly reduce the area and delay of FCN layouts. Furthermore, his hexagonalization enables the transfer of knowledge from the QCA domain to SiDB layouts 🤯 like our new SAT-based clock number assignment algorithm.

In an effort to bring the worlds of physics and design automation closer together, we enable atomic defect-aware physical design to evade material imperfections during placement and routing. Many thanks to @jeremiah-croshaw for the collaboration!

Miscellaneous

As always, we smashed bugs wherever we found them 🐛 we worked on usability, improved performance, updated all libraries to their latest versions, overhauled the documentation and build system, extended the CI setup, and reached 98%+ code coverage on CodeCov ☂️ Many more changes small and big hide in the full release notes. Check them out below. Thanks here go to @wlambooy and @hibenj who made their first contributions 🎉

Full CHANGELOG: v0.5.0...v0.6.0

Many thanks to all contributors!

✨ Features and Enhancements

• 🎨 Refactored the technology mapping interface @marcelwa (#278)
• ✨ Wiring reduction @simon1hofmann (#367)
• 🐍 Added Python bindings @marcelwa (#371)
• ✨ H-Si(111)-1x1 surface support @Drewniok (#380)
• ⚗️ Added the clock number assignment experiment scripts @marcelwa (#394)
• 🎨 Usability improvement by return type adjustments @marcelwa (#395)
• ✨ SAT-based clock number assignment @marcelwa (#381)
• ✅ Add more tests for 3-state simulation. @Drewniok (#374)
• ✨ Added an upper bound option for the total layout area to exact @marcelwa (#360)
• ✨ Added 'Ripple' to the list of supported clocking schemes @marcelwa (#358)
• 📝 Added an SiDB simulation figure to the README @marcelwa (#359)
• ✨ Compile time flows and CLI simulation update @marcelwa (#349)
• 🪝 Set up pre-commit checks @marcelwa (#341)
• 🎨 Allow fiction coordinates for simulation and other functions. @Drewniok (#336)
• ✨ Benchmark for physical simulators. @Drewniok (#338)
• ✨ MIG inverter optimization and propagation @marcelwa (#248)
• ⚗️ Updated the atomic defect-aware SiDB physical design experiment in accordance with the final paper @marcelwa (#330)
• ✨Refactored the hexagonalization algorithm @simon1hofmann (#316)
• 🎨 support cds as input for all simulators @Drewniok (#310)
• ✨ Gate-level layout file reader and writer @simon1hofmann (#296)
• ✨ Support defects in the SiDB Gate Designer @Drewniok (#289)
• 🏗️ Overhauled and modernized the build system @marcelwa (#288)
• ✨ SiDB Gate Designer @Drewniok (#282)
• ✨ Post-Layout Optimization @simon1hofmann (#260)
• ✨ SiDB Operational Domain Computation @marcelwa (#255)
• ✨ New SiDB simulator QuickExact and simulation of atomic defects. @Drewniok (#203)
• ✨ Enhanced pathfinding versatility @marcelwa (#279)
• ✨ Added function to generate random SiDB layouts and write simulation results to file. @Drewniok (#200)
• ✨ Support defects in SiQAD coordinates for layout reading and writing @Drewniok (#269)
• ✨ Support defects in print function. @Drewniok (#261)
• 🎨 Use unit library for sidb defects. @Drewniok (#254)
• ✨ Added additional distance functions and distance maps @marcelwa (#250)
• ✨ Added a library for data types of units used within the physical simulation algorithms @Drewniok (#236)
• ✨ Added a unified print_layout function @marcelwa (#240)
• ✨ Add function to generate a random coordinate. @Drewniok (#233)
• ✨ Added a hexagonalization algorithm for mapping QCA layouts to SiDB ones @simon1hofmann (#198)
• ✨ SiQAD coordinate iteration @wlambooy (#223)
• ✨ Add ISCAS85 and EPFL benchmarks @simon1hofmann (#221)
• ✨ Enable charge layout printing @wlambooy (#219)
• ✨ Temperature-aware physical SiDB simulation @Drewniok (#120)
• ✨ Make ClangFormat aware of different line ending types and enforce LF @marcelwa (#177)
• ✨ Added an SiDB simulation file writer @marcelwa (#176)
• ✨ Added a function to round a number to n decimal places @Drewniok (#189)

⚡️ Performance

• ⚡ Increased parallelism for building and testing in the Ubuntu and Windows workflows @marcelwa (#370)
• 🎨 Fix minor oversights by using static constexpr and noexcept @marcelwa (#306)
• ⚡ Use mold instead of ld for faster link times @marcelwa (#210)

🐛 Bug Fixes

• 🎨 Consistency fixes for pyfiction and the documentation @marcelwa (#427)
• 🎨 Refactored the technology mapping interface @marcelwa (#278)
• 🐛 Fixed conversion of cube coordinate with negative y-value to SiQAD coordinate @Drewniok (#410)
• 🐛 Include x_min and y_min in OpDomain and check non-emptyness of vector before accessing element. @Drewniok (#407)
• 🎨 Usability improvement by return type adjustments @marcelwa (#395)
• 🐛 Fixed an inconsistency in SiDB layout printing @marcelwa (#396)
• 🐛 Fixed bug in three-state simulation and duplicate cds results for QuickExact. @Drewniok (#388)
• 🐛 Add round-function to mitigate floating precision issues @Drewniok (#375)
• 🐛 Fixed hop energy calculation from neutral to positive SiDB @Drewniok (#364)
• 🐛 Fix floating-point errors. @Drewniok (#363)
• 🐛 read_sqd_layout now updates the aspect ratio properly for SiQAD-coordinate based layouts @wlambooy (#355)
• 🐛 Atomic defect can be updated or new one can be assigned at specific coordinate. @Drewniok (#354)
• 💚 Fix for MacOS CI @Drewniok (#353)
• 💚 Hotfix for the macOS CI @marcelwa (#352)
• 🐛 The critical temperature value will only be overwritten by the new value if the new value is lower. @Drewniok (#343)
• 🐛 Place inputs and outputs in the same order during hexagonalization @simon1hofmann (#342)
• ☂️ Added Codecov configuration file @marcelwa (#339)
• 📁 Case style of experiments folders corrected in fiction_experiments.hpp @hibenj (#337)
• 🐛 Algorithm name is written correctly to stats. @Drewniok (#335)
• 🐛 Correct y-direction boundary for Moore neighborhood @Drewniok (#331)
• 🎨 Fix urgent CodeQL warnings. @Drewniok (#329)
• ⚗️ Updated the atomic defect-aware SiDB physical design experiment in accordance with the final paper @marcelwa (#330)
• 🐛 The dependent cell is now linked correctly to the simulation base number in SiDB simulation @Drewniok (#326)
• 🐛 Fixed a bug that caused pre-mature termination of sidb_surface_analysis @marcelwa (#327)
• 💚 Fix VSC builds @marcelwa (#320)
• 🐛 Fixed design-rule violation testing and equivalence checking on empty gate-level layouts @marcelwa (#309)
• 🎨 Fix minor oversights by using static constexpr and noexcept @marcelwa (#306)
• 🔧 Updated the linguist attributes @marcelwa (#301)
• 🔧 Fix broken CodeQL Pipeline @simon1hofmann (#303)
• 👷 Fix Windows CI @marcelwa (#294)
• 🚨 Fix compiler warnings and more consistency @Drewniok (#283)
• 🐛 Fixed a nullptr dereference bug @marcelwa (#287)
• 🐛 Fix docume...

v0.5.0

Fiction is a way to challenge the status quo and to push the boundaries of conventional thinking. — unknown

👀 What's Changed

This latest version of fiction constitutes a whole year of our research efforts, which we condensed into this open-source platform for the FCN community to build upon. Following last year's rework, we have greatly extended fiction's header-only library with new algorithms and data structures.

Thanks to @Drewniok's efforts and @samuelngsh's support, we have introduced the capability to physically simulate SiDB layouts both heuristically and exhaustively for the first time in fiction. In addition, we have integrated the SiDB Bestagon gate library to obtain cell-level SiDB layouts from placed and routed gate-level descriptions, and improved the interoperability with SiQAD by enabling the parsing of SQD files.

Moreover, we have added a comprehensive path-finding and routing library that supports well-established algorithms from the literature, including A*, JPS, and Yen's algorithm, as well as our own multi-path routing algorithm, color routing. Among these new additions are also a graph coloring engine and a generic function optimizer based on simulated annealing that are useful in many design automation contexts.

Furthermore, we have added support for the molecular FCN simulator SCERPA (many thanks to Giuliana Beretta!), the CFE clocking scheme, parallel STL algorithms, performance improvements across many core data structures, an expanded CI setup, and much more.

Full CHANGELOG: v0.4.0...v0.5.0

Many thanks to all contributors!

✨ Features and Enhancements

• ✨ Added a generic function optimizer based on Simulated Annealing @marcelwa (#148)
• ⚡ Search space reduction in SiDB simulation @Drewniok (#150)
• 🎨 added a new function get_chargeless_potential_between_sidbs @Drewniok (#138)
• ✨ Release Drafter to automatically maintain a Draft Release @Drewniok (#139)
• 📝 Added GitHub templates @marcelwa (#133)
• 👷 Updates to the CI platform @marcelwa (#132)
• ✨ Added conversion functions for layouts of different coordinate types @Drewniok (#125)
• ✨ Added multi-threading support for QuickSim @Drewniok (#128)
• 📝 Revised the README badges @marcelwa (#127)
• ✨ Added a Verilog writer to the CLI @marcelwa (#115)
• ✨ Added a framework for accurate and efficient simulation of SiDB logic @Drewniok (#105)
• ✨ Added a framework to represent and handle SiDB defects @marcelwa (#103)
• ✨ Multi-Path Signal Routing @marcelwa (#83)
• 📝 Improvements to the README and documentation @marcelwa (#77)
• 👷 Added a ClangFormat linter workflow @marcelwa (#75)
• 👷 Run CI only when necessary @marcelwa (#73)
• 👷 Added a workaround for empty review messages in the clang-tidy-review workflow @marcelwa (#70)
• 🎨 Set up a consistent clang-tidy workflow together with a designated CI code review process @marcelwa (#64)
• 👷 Activate experiments in CIs to ensure they're building @marcelwa (#63)
• 👷 Enable ccache for GitHub Action runners @marcelwa (#60)
• 🎨 Switched static constexpr for inline constexpr at file-scope @marcelwa (#59)
• 👷 Z3 setup action @marcelwa (#58)
• 🎨 Layout technology traits @marcelwa (#53)
• 👷 Enabled automatic linking with TBB when compiling with GCC to enable parallel STL algorithms @marcelwa (#57)
• ✨ QLL writer for mQCA (MagCAD & SCERPA) @marcelwa (#49)
• ✨ Added the CFE clocking scheme @marcelwa (#44)
• ♻️ Refactored the CMake build system @marcelwa (#42)
• ⚗️ Added experimental data of the Bestagon paper @marcelwa (#33)
• ✨ Added the SiDB Bestagon gate library @marcelwa (#32)

⚡️ Performance

• ⚡ Utilize std::string_view instead of std::string in many places to improve performance @marcelwa (#153)
• ⚡ Search space reduction in SiDB simulation @Drewniok (#150)
• ✨ Added multi-threading support for QuickSim @Drewniok (#128)
• ⚡ Improved performance by switching to phmap in more places @marcelwa (#118)

🐛 Bug Fixes

• ✅ Made the DOT drawer tests independent of the version number @marcelwa (#170)
• 📝 Fixed some inconcistencies in the RTD documentation @marcelwa (#167)
• 🐛 Removed excess template parameter typename T @simon1hofmann (#162)
• 🚨 Fixed error message from multiple IPO Checks @lsschmid (#157)
• 🚨 Fixes for linker errors and CMake name collisions @marcelwa (#154)
• 🚨 Fixed warnings and notes brought up by CodeQL @marcelwa (#151)
• 📝 Fixed namespace in SiQAD utility function documentation @marcelwa (#152)
• 📝 Updated notes on the installation process to the documentation @marcelwa (#149)
• 🐛 Prevent manually declared layout obstructions to be cleared by the application of Yen's Algorithm @marcelwa (#143)
• 🎨 added a new function get_chargeless_potential_between_sidbs @Drewniok (#138)
• 🎨 CI inconsistency fixes @marcelwa (#142)
• 👷 Changed CI name @marcelwa (#141)
• 🩹 Renamed functions to more appropriately reflect their role @Drewniok (#135)
• 🐛 Fixed accessing non-existing variables in potential_between_sidbs @marcelwa (#134)
• 🎨 doxygenfunction of quicksim was under the wrong header @Drewniok (#129)
• 🐛 std::rand replaced by std::mt19937_64 @Drewniok (#124)
• 🎨 Small inconsistency fix @marcelwa (#123)
• 🐛 Fixed a bug in crossing considerations of obstruction_layouts @marcelwa (#122)
• 🐛 Added additional checks for is_obstructed_connection to ensure proper handling of crossing cases @marcelwa (#117)
• 🐛 Updated the routing utils to fix a bug in crossing wire detection @marcelwa (#116)
• 🎨 Fixed a few inconsistencies @marcelwa (#114)
• 🔥 Removed unnecessary Catch2 CMake call @marcelwa (#112)
• 🐛 Fixed a bug in color_routing @marcelwa (#113)
• 🐛 Fixed several I/O issues @marcelwa (#111)
• 🐛 Fixed duplicate crossing cells in the iNML technology @marcelwa (#110)
• 🐛 Fixed a bug in the clear_tile function that lost track of PI and PO count @marcelwa (#104)
• 👽 Updated the QLL layout writer regarding recent changes in the mQCA format @marcelwa (#102)
• 🐛 Fixed a bug in SAT-based graph coloring (this time for real) @marcelwa (#101)
• 🐛 Fixed a bug in SAT-based graph coloring @marcelwa (#100)
• 🐛 Fix number regex @marcelwa (#88)
• 💚 Switched to single-threaded CI build due to memory issues on the runners @marcelwa (#86)
• ⚡ Made distance functions constexpr @marcelwa (#85)
• 💚 Fixed GitHub Actions' wildcard paths resolves @marcelwa (#81)
• 💚 Added fixes for MSVC 2022's C2760 and C3878 by utilizing type specifiers instead of types for casting and variable declaration @marcelwa (#82)
• 👷 Added a workaround for empty review messages in the clang-tidy-review workflow @marcelwa (#70)
• 👷 Split the clang-tidy review workflow into two separate ones @marcelwa (#69)
• 🐛 Fixed a bug with layout DOT drawers and a small inconsistency in the tests @marcelwa (#66)
• 👷 Activate experiments in CIs to ensure they're building @marcelwa (#63)
• 💚 Added a macOS CI workaround to fix an issue with XCode 14.0 @marcelwa (#61)
• 🚚 Renamed the ESP clocking scheme to ESR @marcelwa (#51)
• 💚 Upgraded toolset to v143 for Visual Studio 2022 CI builds @marcelwa (#50)
• 🔧 Updated the Dockerfile @marcelwa (#48)
• 🐛 include cell_ports in fcn_gate_library.hpp @Drewniok (#43)
• 🚨 Make sure the Bestagon experiment is not compiled if Z3 is not found @marcelwa (#36)
• 🐛 Fixed a compilation bug that could occur by including the same header multiple times @marcelwa (#34)

📝 Documentation

• 📝 Update the CHANGELOG to include the latest changes @marcelwa (#169)
• 📝 Fixed some inconcistencies in the RTD documentation @marcelwa (#167)
• 📝 Fixed namespace in SiQAD utility function documentation @marcelwa (#152)
• 📝 Updated notes on the installation process to the documentation @marcelwa (#149)
• 📝 Updated the list of implemented design automation algorithms @marcelwa (#144)
• ✨ Release Drafter to automatically maintain a Draft Release @Drewniok (#139)
• 📝 Added GitHub templates @marcelwa (#133)
• 🎨 doxygenfunction of quicksim was under the wrong header @Drewniok (#129)
• 📝 Revised the README badges @marcelwa (#127)
• 📝 Added RST documentation for the SiDB simulation framework @marcelwa (#109)
• 📝 Updated documentation @marcelwa (#87)
• 📝 Improvements to the README and documentation @marcelwa (#77)
• 📝 Added CodeQL, Docker, and Clang-Tidy badges to the README @marcelwa (#65)
• 📝 Bestagon bibliography @marcelwa (#56)

✅ Testing

• ✅ Made the DOT drawer tests independent of the version number @marcelwa (#170)
• 🎨 Restructured sidb_charge_state and added tests @marcelwa (#168)
• ✅ Added unit tests for ExGS and QuickSim @Drewniok (#136)
• 🩹 Renamed functions to more appropriately reflect their role @Drewniok (#135)
• ✅ Added tests for STL utils @marcelwa (#119)

👷 CI

• 👷 Updated compilers on GitHub Actions to match latest runner versions @marcelwa (#166)
• ⬆️ Bump ZedThree/clan...

v0.4.0

There are people who think that things that happen in fiction do not really happen. These people are wrong. — Neil Gaiman

This release states the largest update to fiction yet. Its architecture has been completely reworked to create a platform upon which the FCN community can build. To this end, fiction now provides

1. a header-only template library that can be utilized in third-party projects,
2. a framework for experiments for rapid prototyping and reproducible findings, and
3. the established CLI that is now built with fiction's new library.

Furthermore, the build system has been revised and third-party dependencies have been cut to leave behind only what was really necessary. No more Boost means less trouble compiling on any system. Z3 is now an optional dependency that, if installed, enables additional features.

Finally, there is a whole lot of new features including but not limited to support for the Silicon Dangling Bond (SiDB) technology and the SiQAD simulator (many thanks to Samuel Sze Hang Ng for the collaboration!) as well as the QCA-STACK tool for 3D QCA circuits (many thanks to Willem Lambooy for the collaboration!), the integration of a technology mapper (many thanks to Alessandro Tempia Calvino for his support!), layout types with hexagonal tiles, and much more.

To learn more about the latest features, see the full CHANGELOG. To get started with writing your own tool built with fiction, check out the DOCUMENTATION.

v0.3.2

This version adds a novel One-pass Synthesis algorithm for Physical Design that combines logic synthesis and placement & routing into a single step. Many thanks to Winston Haaswijk for the collaboration on this project! The new command can be executed via onepass. For further information, refer to the paper "One-pass Synthesis for Field-coupled Nanotechnologies" in ASP-DAC 2021.

Additionally, this release includes updates to libraries and the build system alongside the novel tt_reader and csv_writer classes for experimental evaluations. To learn more, see the full CHANGELOG.

v0.3.1

This latest iteration of the fiction framework aims at performance, stability, and usability improvements on many levels. Inspired by Alan Mishchenko's work, exact has been completely reworked to gain significant performance improvements (up to 50% on some benchmarks) and support for parallelism that helps with larger circuit layouts. Also, ortho has been optimized to no longer need to post-process layouts.

Additionally, the code from our latest paper "Verification for Field-coupled Nanocomputing Circuits" in DAC 2020 is available in this release to perform equivalence checks between layouts and specifications. Further additions include but are not limited to new commands for energy and area calculations, further flags for existing algorithms, build improvements, and fixes for all reported bugs. To learn more, see the full CHANGELOG.

v0.3.0

Proudly announcing a collaboration with Umberto Garlando from Politecnico di Torino on this latest release to bring first support for in-plane Nanomagnet Logic and integration with ToPoliNano and MagCAD. Additionally, this version comes with built-in logic synthesis and simulation using the wonderful EPFL Logic Synthesis Libraries, design rule checking for gate-level layouts, new parameters to tweak existing algorithms, dozens of performance optimizations, and much more. For further information, see the full CHANGELOG.